Design Considerations of Voltage Programming Pins

6.2.1. OTP Memory Cells

To electrically program the OTP memory cells, Fig. 6.1 depicts the required bias conditions on the memory unit (NMOS cell) which has a control gate and a floating gate. Before programming, there is no or only a few charges in the floating gate. Original threshold voltage of a non-programmed NMOS cell is defined as Vt0. Vt0 is smaller than 5 V so that the NMOS cell can be turned on (channel can be induced) when the control gate is biased at 5 V (Fig. 6.1(a)). To program the NMOS cell, a high gate bias of 12.5 V (VPP voltage) is applied on the control gate and the drain of NMOS cell is biased at VDD of 5 V. With the high gate bias of 12.5 V on the control gate, electrons permitted from the source can pass through the insulating layer beneath the floating gate to be accumulated in the floating gate (Fig. 6.1(b)).

After a span of field programming time, the 12.5 V VPP voltage is removed and the electrons that accumulated in the floating gate are trapped in the floating gate. The trapped electrons in the floating gate can substantially increase the threshold voltage of the NMOS cell from Vt0

to Vt’. As long as the number of electrons trapped in the floating gate is large enough (the programming time is long enough), Vt’ can be higher than 5 V. Consequently, the channel of NMOS cell can no longer be induced by the 5 V gate bias, and the NMOS cell becomes an open circuit after programming, as shown in Fig. 6.1(c). By exploiting this principle, on-chip memory arrays can be programmed to represent different digital codes to calibrate IC products or to predefine different IC functions to broaden their application scopes [125].

6.2.2. VPP Programming Waveforms

To design an ESD protection circuit for voltage programming pins, it is essential to understand the VDD and VPP programming waveforms. The typical measured VDD and VPP

programming waveforms are shown in Fig. 6.2. Under the VPP programming condition, VDD

voltage is charged up from 0 to 5 V before the set in of VPP voltage ramping, so that internal circuits such as control logic or address decoder can function properly. After the VDD voltage has been charged to 5 V, the programmer pulls high the VPP voltage from 0 to 12.5 V, as shown in Fig. 6.2.

Fig. 6.2. Measured voltage waveforms on VDD and VPP pins during programming.

To comprehensively protect I/O pins against ESD stresses, a typical rail-based ESD protection scheme is shown in Fig. 6.3, where two diodes DU and DN are used to divert ESD stress energy at the I/O pad to the VDD or the GND power supply lines. Because the power-rail ESD clamp circuit is especially designed with a large ESD protection device (MN4), it is effective in discharging ESD energy between power supply lines. Through the DU

and DN diodes in cooperation with the power-rail ESD clamp circuit, the rail-based ESD protection scheme has been reported as an effective method to significantly improve ESD robustness of the I/O pin. However, since the 12.5 V VPP voltage is higher than the 5 V VDD

voltage during programming, the diode DU that diverts the high VPP voltage to the VDD power supply line is prohibited. Otherwise, the memory cells cannot be successfully programmed due to insufficient voltage on the VPP pin. Without the diode DU, power-rail ESD clamp

circuit cannot help discharge ESD energy at the I/O pad under PS- and PD-mode ESD tests.

Accordingly, I/O pins without a forward diode from the I/O pad to the VDD power supply line usually have a low ESD protection level, especially under PS- and PD-mode ESD tests.

Mixed-voltage I/O buffers where I/O voltages would be higher than their VDD voltages suffered the same limitation, too[126].

Fig. 6.3. Traditional whole-chip ESD protection scheme with the power-rail ESD clamp circuit. The diode DU results in an unwanted leakage current path when I/O voltage is higher than the VDD voltage during some special circuit operating conditions.

Besides the inability of employing power-rail ESD clamp circuit under PS- and PD-mode ESD tests, the rise time of programming voltage on VPP pin (TR,VPP) is another design issue that strongly affects the ESD protection design to VPP pin. Since the VPP programming voltage is externally supplied from a programmer, different programmers may have different driving capabilities to result in huge differences between slew rates of programming voltages on VPP pin. The rise time of VPP programming voltage may be as slow as several microseconds [127], or as fast as several tens of nanoseconds in different programming environments [127], [128]. Because the rise time of ESD voltage has the same timescale to that of fast VPP programming voltage (several tens of nanoseconds), some of traditional ESD

protection designs could be mis-triggered by their ESD trigger circuits. A primary ESD protection PMOS with a RC timer to control its gate voltage was reported to protect the programming pin by Im et al [129]. The RC timer should have a time delay over several hundreds of nanoseconds, so that the gate of ESD protection PMOS can be kept low to turn on PMOS during the ESD transition. However, when the rise time of the VPP programming voltage was also in the same scale as that of ESD transient voltage, the simple RC timer directly connected to the programming pin cannot distinguish between the normal programming event and ESD transition event. The ESD protection PMOS in [129] would be turned on both during VPP programming and ESD transition. The turned-on PMOS during programming event will pull down the VPP voltage to cause a false programming result.

Additional modification should be added into the design of [129] to avoid the false programming issue when the programmer provides the VPP programming voltage pulse with a fast rise time. To avoid the mis-triggering issue and make ICs comprehensively compatible to programmers from different manufacturers, a wide range of acceptable VPP voltage rise time during programming is requested by customers.

Fig. 6.4. Previous ESD protection design for V_PP pin. It can be safely programmed with fast V_PP voltage rise time but has a lower ESD protection level of only 2 kV in HBM.

6.2.3. Previous ESD Protection Designs for VPP Pins

A previous ESD protection design for VPP pin used in some IC product is shown in Fig.

6.4. Without any ESD trigger circuit in this ESD protection design, both the ESD protection devices, FOD (field oxide device) and the diode DN, are insensitive to the rise time of VPP

programming voltage. Under ND- and NS-mode ESD tests, the power-rail ESD clamp circuit and the diode DN provide effective ESD discharging paths. Under PS-mode ESD test, ESD voltage induces breakdown of the diode DN to conduct ESD current through the reverse-biased junction of DN. A FOD device is placed between the VPP pin and the VDD line, so that PD-mode ESD energy can be directly discharged to the grounded VDD line through the n-p-n bipolar junction transistor (BJT) inherent in the FOD [130]. Because the diode inherent in the FOD device has a breakdown voltage higher than 12.5 V, the FOD device does not result in current path from the VPP pin to the VDD line during programming. Under PS-mode ESD test, FOD can help divert some ESD energy to the VDD line, and it can be further discharged to the grounded GND through the power-rail ESD clamp circuit. By using this previous ESD protection design, the measured HBM ESD protection level on VPP pin is only 2 kV verified in an IC product.

Fig. 6.5. SEM image of the previous ESD protection design after 2.5-kV PS-mode ESD test. ESD failure locations were found on both the FOD device and the diode DN.

SEM image of the previous ESD protection design after 2.5-kV PS-mode ESD test is shown in Fig. 6.5. ESD failure locations were found on both the FOD device and the diode DN. The failure analysis verified that the FOD device can help discharge ESD energy under PS-mode ESD test. The previous ESD protection design can provide the typical HBM ESD protection level of 2 kV to the IC product, but the specified HBM ESD protection level has recently been increased from 2 to 4 kV by customers with high reliability requirement. For lack of ESD trigger circuit in the previous ESD protection design, further enlarging the device width of FOD did not improve HBM ESD protection level due to the well-known non-uniform triggering phenomenon [26]. Moreover, for cost reduction, silicide blocking (SB) was not used in such IC products. Without silicide blocking, severe current crowding phenomenon and current filamentation further deteriorate the linearity of ESD robustness to the device dimension of an ESD protection device. ESD trigger techniques have been reported to effectively relieve the negative impact on ESD robustness due to silicidation.

Accordingly, with the inability to meet the new requirement of 4-kV HBM ESD protection level by the previous ESD protection design, a new ESD protection design is therefore requested and proposed. The new proposed ESD protection design can not only exploit the ESD trigger technique to achieve high ESD robustness, but also avoid the mis-triggering of ESD protection device under VPP programming voltage with a fast rise time.