Fully-Silicided I/O Buffer Without Ballasting

In nowadays CMOS ICs, to minimize the required layout area for I/O buffers, self-protected I/O design (I/O buffer without additional ESD protection devices) is usually adopted. Layout of the self-protected I/O buffers in a CMOS IC product is shown in Fig. 5.5.

Gate length in the I/O buffer is increased to avoid the reverse channel length dependency [114]. Device dimension of the driver NMOS (MN1) is 480 m / 1.25 m with each finger width of 40 m, and device dimension of the driver PMOS (MP1) is 360 m / 1.25 m with each finger width of 30 m. Both NMOS and PMOS have drain contact to poly gate edge

(Dcg) of 4.75 m, which is originally drawn for silicide-blocking rules. However, to reduce the fabrication cost, no silicide-blocking is adopted in the given CMOS process for IC production. The main ESD protection NMOS in the active power-rail ESD clamp circuit has the same layout style as that of the driver NMOS in I/O buffer.

TABLE5.1

ESDROBUSTNESS AMONG THE I/OBUFFERS

ESD test results in Table 5.1 show that the fully-silicided I/O buffers without ballasting failed to pass the essential ESD specification of 2-kV HBM ESD stresses. Among the ESD measurements of the un-ballasted I/O buffers, PS-mode ESD test has the lowest ESD protection level. Under the PS-mode ESD stresses, the ESD current is first discharged to VDD

through the forward diode DP inherent in MP1, and to the grounded VSS through the power-rail ESD clamp circuit. In spite of the gate driven technique to enhance turn-on speed of the power-rail ESD clamp circuit during ESD stresses [115], [116], the overshooting voltage on the I/O pad cannot be completely suppressed due to the inevitable turn-on resistance of devices and interconnects. Consequently, for lack of proper ballasting design, when the overshooting voltage on the I/O pad induces breakdown on the fully-silicided driver NMOS, it is easily filamented due to severe current crowding and non-uniform triggering.

Fig. 5.6. SEM image of the fully-silicided I/O buffer without ballasting after 2-kV PS-mode ESD stress. ESD failure is found on only one finger of the driver NMOS. Current filamentation is also observed on the surface of the driver NMOS without ballasting.

SEM image of the un-ballasted I/O buffer after 2-kV PS-mode ESD stress is shown in Fig.

5.6, where the trace of current filamentation is found on the driver NMOS. The failure analysis (FA) result has verified that the driver NMOS is driven into breakdown during the 2-kV PS-mode ESD test. Non-uniform triggering among the multiple fingers of the un-ballasted driver NMOS can also be clearly observed in Fig. 5.6, since ESD failure only locates on one of the fingers. The surface burned-out trace from drain to the grounded source further indicates insufficient ballast resistance to make ESD current crowding within limited shallow depths. Accordingly, the Dcg spacing of 4.75 m in a fully-silicided NMOS is insufficient to provide adequate ballast resistance due to the small sheet resistance from silicides.

5.3.2. I/O Buffer with N-Well Ballasting Technique on Driver NMOS

To enhance the PS-mode ESD robustness, the N-Well ballasting technique was applied to the driver NMOS of I/O buffer [95]. The main ESD protection NMOS (MN2) in the active

power-rail ESD clamp circuit was also implemented with N-Well ballasting. The driver PMOS was still left un-ballasted in this test. Fig. 5.7 shows the diagram of the I/O buffer with a sketch of its metal connection to the I/O pad. To keep the same cell width of I/O buffers in IC chips, both Dcg spacing and gate length are kept the same as those in the I/O buffers without ballasting. Spacing for island diffusion and drain diffusion is 1.75 m in layout. In the I/O buffers with N-Well ballasting, each finger width of driver NMOS is 30 m, and each finger width of driver PMOS is 25 m. The total device dimension (W/L) of NMOS (PMOS) in I/O buffer is 360 m / 1.25 m (300 m / 1.25 m). Driver NMOS with ballast N-Well in this test was laid out with truncation to the island diffusions to prevent ESD damage from the tips of N+ island diffusions to the P+ guard ring. With the foundry-provided N-Well sheet resistance of 800/ , the overall resistance imposed on NMOS (with 12 fingers in parallel) due to the ballast N-Well is 800 (1.75 m/30 m)12 = 3.88 . With the operating frequency specification of 20 MHz, the driving capability can be effectively compensated by transistor sizing to meet the desired specification of I/O applications. For example, the output resistance of a driver NMOS with 12-mA driving specification is 0.4 V  12 mA = 33.33 , which is much higher than the 3.88-parasitic resistance from ballast N-Well.

Moreover, the parasitic junction capacitance (Cj) and sidewall capacitance (Cjsw) of N-Well/P-Substrate junction are 1.08 10^-4 and 7.32  10^-4 pF/m, respectively. Cj and Cjsw

of N+/P-Substrate junction are 6.19  10^-4 and 2.58  10^-4 pF / m, respectively. Although the Cjsw value for N-Well is higher than the Cjsw value for N+ diffusion, the Cj value for N-Well is much lower than the Cj value for N+ diffusion due to the larger depletion width of N-Well/P-Substrate junction. For self-protected driver NMOS, due to the large device width and the increased drain contact to poly gate spacing, the Cj value will take a major portion in the overall junction capacitance. As a result, the added capacitance due to ballast N-Well can be small and does not affect the I/O operating frequency specification of 20 MHz.

Fig. 5.7. Diagram to show the metal connection to the I/O pad for the driver NMOS with ballast N-Well but the driver PMOS without ballasting.

ESD measurement results for the I/O buffers with N-Well ballasting technique are shown in Table 5.1. Although N-Well ballasting technique substantially increases PS-mode ESD robustness to 7 kV, the 4-kV ND-mode ESD test result has become the bottleneck for the I/O buffers to achieve the performance target of 6-kV HBM ESD robustness.

During the ND-mode ESD tests, ESD current is discharged through the power-rail ESD clamp circuit and the forward diode DN inherent in the driver NMOS. As a result, the voltage across the VDD and I/O pad is

ΔVND = [IESD × (Ron, Power-Rail + RVSS + Ron, DN) + Vt, DN] , (5.1) where the Ron, Power-Rail and Ron, DN denote the turn-on resistance of power-rail ESD clamp circuit and the diode DN during ESD stresses; RVSS denotes the effective resistance of the VSS

interconnection, and Vt, DN is the cut-in voltage of the diode DN. At high IESD level, i.e. high ESD stress voltage, the ΔVND can exceed Vt1 of the driver PMOS and induce triggering of the parasitic PNP BJT in the PMOS. As a result, part of the ESD current is discharged through the driver PMOS under high ESD current conditions. For lack of proper ballasting, ESD

current discharged through the driver PMOS is crowded within the shallow surface, which further deteriorates the ESD robustness of driver PMOS. For I/O buffers with N-Well ballasting technique on driver NMOS, the PMOS has smaller device width than that in the fully-silicided I/O buffers. Accordingly, though driver PMOS in the two structures are both fully-silicided without ballasting, I/O buffer with N-Well ballasting technique on driver NMOS has lower ND-mode ESD robustness (4 kV) compared to ND-mode ESD robustness of fully-silicided I/O buffer without ballasting (4.5 kV).

SEM image of the I/O buffer after 4.5-kV ND-mode ESD stress is shown in Fig. 5.8.

Current traces from source of the driver PMOS toward its drain regions are observed, which confirms that breakdown of the un-ballasted driver PMOS is the limitation to ESD robustness of I/O buffer with N-Well ballasting technique. Failure spots are found within more than one of the PMOS fingers because PMOS devices barely exhibit snapback phenomenon in deep-submicron CMOS technologies [86].

Fig. 5.8. SEM image of the fully-silicided I/O buffer with N-Well ballasting technique on the driver NMOS after 4.5-kV ND-mode ESD stress. Failure locations are found on the driver PMOS due to the triggering of parasitic BJT in PMOS.

Fig. 5.9. Diagram to show the metal connection to the I/O pad for the driver NMOS realized with type-A layout scheme.

Fig. 5.10. Cross-sectional view along A-A’ line of the fully-silicided I/O buffer realized with the type-A layout scheme.

5.4. New Layout Schemes for Fully-Silicided I/O Buffers

Though the N-Well ballasting technique prevents PS-mode ESD failure on the driver NMOS and increases the whole-chip ESD protection level from 1.5 to 4 kV, it still fails to meet the adequate performance target of 6-kV HBM ESD robustness. From the ESD

measurement and FA results, ballasting technique on the driver PMOS is vital to the improvement of ESD robustness on fully-silicided I/O buffers. As a result, two new layout schemes are proposed to ballast both NMOS and PMOS devices in the I/O buffer. The new proposed designs have been verified in some IC products fabricated in the same 0.35-m 5-V fully-silicided CMOS process, and have been confirmed with substantial improvement on the whole-chip ESD protection level.

5.4.1. I/O Buffer with The New Proposed Layout Scheme (Type A)

To provide efficient ballast on the driver PMOS, Fig. 5.9 shows the diagram of type-A layout scheme. The driver NMOS in the type-A layout scheme is drawn with N-Well ballasting. However, the drain of the driver PMOS is not connected directly to the I/O pad.

Instead, drain of the PMOS is connected to the drain diffusion of the driver NMOS, which is electrically connected to the I/O pad by means of the ballast N-Well. The driver NMOS and PMOS in the type-A layout scheme have the same device dimensions as those in the I/O buffers with N-Well ballasting technique on driver NMOS. The main ESD protection NMOS (MN2) of the power-rail ESD clamp circuit in this scheme is N-Well ballasted. Device cross-sectional view along A-A’ in Fig. 5.9 is shown in Fig. 5.10. It can be understood from Fig. 5.10 that only the island diffusion of the driver NMOS is directly connected to the I/O pad. Through such a layout arrangement, PMOS current is forced to flow through the N-Well ballast resistor in the driver NMOS, enforcing the N-Well to ballast both driver NMOS and PMOS during ESD stresses.

In the type-A layout scheme, the ESD current under PS-mode ESD tests first flows to the floating VDD through the N-Well ballast resistor and the DP diode. Then, the ESD current is discharged to the grounded VSS through the power-rail ESD clamp circuit. Under the PD-mode ESD tests, the ESD current is first discharged to the grounded VDD through the N-Well ballast resistor and the DP diode. Therefore, voltages across the stressed I/O pad and

ground under the PS- and PD- mode ESD tests are

ΔVPS = [IESD × (Rballast + Ron, DP + RVDD + Ron, Power-Rail) + Vt, DP] (5.2) and

ΔVPD = [IESD × (Rballast + Ron, DP + RVDD) + Vt, DP] . (5.3)

Fig. 5.11. TLP-measured I-V curves for the I/O buffer with the type-A layout scheme. The tests were manually stopped at 2 A without causing failure to the I/O buffer.

With the ESD current being forced to flow through the N-Well under PS- and PD- mode conditions, it has been reported that the N-Well resistor under high current level exhibits high resistance characteristic due to drift velocity saturation [97]. As the TLP measurement results shown in Fig. 5.11, under PS-mode (positive TLP stress on I/O pad with VSS relatively grounded) and PD-mode (positive TLP stress on I/O pad with VDD relatively grounded) TLP measurements, the drift velocity saturation results in the 24-V voltage at IESD of 0.5 A. The applied voltage is mainly dropped within the N-Well region. At the same time, electron-hole pairs are generated to support the increased current, and electric field is built up toward the N+ island diffusion/N-Well junction. The electric field build-up eventually results in

avalanche breakdown to happen at the N+/N-Well junction, which results in the snapback as observed in Fig. 5.11. With the avalanche breakdown at N+/N-Well junction, the hole concentration can exceed the background doping of N-Well, and results in conductivity modulation to lower the turn-on resistance of N-Well [116], [117]. For NS-mode (positive TLP stress on VSS pin with I/O pin relatively grounded) and ND-mode (positive TLP stress on VDD pin with I/O pin relatively grounded) TLP measurements, ESD currents are discharged through the DN diode and the power-rail ESD clamp circuit (in ND-mode test) without flowing through the ballast N-Well. Therefore, the high resistance characteristic from N-Well is not observed in the ND- and NS- mode TLP I-V curves in Fig. 5.11.

Fig. 5.12. SEM image of the fully-silicided I/O buffer realized with the type-A layout scheme after 6.5-kV PS-mode ESD stress. Uniformly distributed N+-to-N-Well ESD damages are found on the driver NMOS.

HBM ESD measurement results in Table 5.1 show that the fully-silicided I/O buffers with the type-A layout scheme have the PS- and PD-mode ESD protection levels as high as 6 kV.

Under the ND-mode ESD tests, though the ΔVND can exceed Vt1 of the driver PMOS under

high ESD stress voltage, the N-Well ballast resistor suppresses the ESD current discharged through the PMOS. Accordingly, fully-silicided I/O buffers with type-A layout scheme have ND-mode HBM ESD robustness over 8 kV. By using the type-A layout scheme, ND-mode ESD failure on the driver PMOS has been successfully overcome and the 6-kV performance target has been achieved.

Among the four ESD test modes on I/O buffers, ESD current under PS- and PD-mode ESD tests has to flow through the ballast N-Well. The N+/N-Well junction breakdown is expected to result in large power dissipation over the ballast N-Well, which results contact spiking on island diffusions of the driver NMOS. With the ESD current flowing from island diffusion through the ballast N-Well to the drain diffusion of driver NMOS, melted metal contacts can result in a short from island diffusion to the drain diffusion of driver NMOS, which results in substantial shift of I-V curve compared to the original I-V curve before ESD stress. The I/O buffer is then judged as a failure because short of island and drain diffusions results in I-V shift over 20% compared to the original I-V curve before ESD stress. The melted metal contacts may also result in a short from island diffusion to the P-Substrate, which can also cause sharp I-V shift after ESD stress. Consequently, the N+-to-N-Well ESD failure has become the limitation to the type-A layout scheme. As the SEM image shown in Fig. 5.12, the I/O buffer after 6.5-kV PS-mode ESD stress shows N+-to-N-Well failure on the driver NMOS. From the uniformly distributed ESD failure locations in Fig. 5.12, the effectiveness of the type-A layout scheme to ballast the I/O buffer for ESD protection has been verified.

5.4.2. I/O Buffer with The New Proposed Layout Scheme (Type B)

In the type-A layout scheme, though the ballast N-Well leads to significant improvement on ESD robustness, it also introduces the (IESD × Rballast) voltage drop to ΔVPS and ΔVPD. The Rballast of N-Well resistor becomes large under high current conditions. The increased (IESD × Rballast) voltage drop pinches the ESD protection window and makes internal circuits more

susceptible to ESD failure. Even though the internal ESD failure was not observed, eliminating the Rballast term in ΔVPS and ΔVPD is also beneficial to the PS- and PD- mode ESD tests. Since the main ESD protection device in a power-rail ESD clamp circuit generally has been drawn with large device dimension, it usually stands much higher ESD stress levels than the NMOS or PMOS in I/O buffers. Furthermore, averting the PS- and PD-mode ESD current from being discharged through the Rballast can further avoid the N+-to-N-Well ESD failure.

Fig. 5.13. Diagram to show the metal connection to the I/O pad for driver NMOS and PMOS in the type-B layout scheme.

To modify the type-A layout scheme and to eliminate the Rballast term under PS- and PD-mode ESD tests, type-B layout scheme is proposed. A diagram is shown in Fig. 5.13 to illustrate the type-B layout scheme, where the N-Well ballast resistor is applied to both driver NMOS and PMOS. Drain of the driver PMOS is separated into drain diffusion and island diffusion by FOX, as shown in Fig. 5.13. Drain diffusions of driver PMOS and NMOS are connected to each other, and island diffusions of both driver PMOS and NMOS are directly

connected to the I/O pad. With such a distinct metal routing in the type-B layout scheme, the P+ island diffusion provides an efficient discharging path for PS- and PD-mode ESD tests, where ESD current can be discharged directly through the DP diode without flowing through the ballast N-Well in NMOS. The cross-sectional view along A-A’ line in Fig. 5.13 is shown in Fig. 5.14. Under the normal circuit operating conditions, with the shorted drain diffusions of driver NMOS and PMOS, PMOS can pull high the I/O pad through the ballast N-Well in the driver NMOS. Device dimensions for driver NMOS and PMOS in type-B layout scheme are the same to those in type-A layout scheme, and I/O buffers with either type-A or type-B layout scheme can meet the operating frequency specification of 20 MHz.

By avoiding ESD current to flow through the ballast N-Well under PS- and PD- mode ESD stresses, the ESD currents are mainly discharged through the diode DP1 and the power-rail ESD clamp circuit (in PS-mode). As the PS- and PD- mode TLP-measured I-V curves shown in Fig. 5.15, high resistance characteristic from the ballast N-Well in type-A layout scheme is avoided in the type-B layout scheme. Therefore, ΔVPS and ΔVPD in the type-B layout scheme are much smaller compared to those in the type-A layout scheme. Under ND-mode and NS-mode conditions, the DN diode and the power-rail ESD clamp circuit are effective in discharging ESD currents, as shown in Fig. 5.15.

Fig. 5.14. Cross-sectional view along A-A’ line of the fully-silicided I/O buffer realized with the type-B layout scheme.

Fig. 5.15. TLP-measured I-V curves for the I/O buffer with the type-B layout scheme. The tests were manually stopped at 2 A without causing failure to the I/O buffer.

Because the ESD current can be discharged without flowing through the ballast N-Well in the driver NMOS, the N+-to-N-Well ESD failure on driver NMOS is avoided in the type-B layout scheme. Moreover, the N-Well can ballast the driver NMOS when ΔVPS or ΔVPS is higher than Vt1,MN1. PS-mode HBM ESD robustness of the I/O buffer has therefore been increased to 7 kV, and the PD-mode HBM ESD robustness has been increased to over 8 kV, as shown in Table I. Emission microscope (EMMI) analysis in Fig. 5.16(a) shows that failure of the I/O buffer with the type-B layout scheme after 7.5-kV PS-mode ESD stress locates on the driver PMOS. The corresponding SEM image of the failure on the driver PMOS in Fig.

5.16(a) is shown in Fig. 5.16(b). Without the ESD damage on source but silicides meltdown on island diffusions, SEM image reveals the PS-mode ESD failure on the P+/N-Well diode (DP) of driver PMOS, which has further confirmed that the type-B layout scheme has taken advantage of the highest whole-chip ESD protection capability from the I/O buffers.

(a)

(b)

Fig. 5.16. (a) EMMI and (b) SEM images of the fully-silicided I/O buffer realized with the type-B layout scheme after 7.5-kV PS-mode ESD stress.

5.5. Summary

Silicidation used in CMOS processes has been reported to cause substantial degradation on ESD robustness of CMOS devices. To mitigate the negative impact on ESD robustness from silicidation, two new ballasting layout schemes for fully-silicided I/O buffers are proposed.