5. New Ballasting Layout Schemes to Improve ESD Robustness of I/O
6.4. Implementation and ESD Testing Results
6.4.3. ESD Measurement Results
Among the ESD current discharging paths, it is known that PS- and PD-mode ESD tests are critical to VPP-pin ESD protection because the ESD current is primarily discharged through the parasitic BJT inherent in the fully-silicided MN2. The proposed ESD protection design under PS-mode ESD stresses was evaluated by using 100-ns TLP system. Failure criterion during TLP test was defined with 1 A leakage current under 5 V bias on VPP pin.
With the substrate-triggered technique, the parasitic BJT inherent in MN2 was triggered on at
~10 V, and the measured secondary breakdown current was 3.8 A, as shown in Fig. 6.11.
Measured HBM ESD protection levels of the IC product equipped with previous ESD protection design (Fig. 6.4) or the new proposed ESD protection design (Fig. 6.6) at VPP pin are summarized in Table 6.2. In the HBM ESD tests, the starting test voltage was 0.5 kV, and the step voltage was 0.5 kV. VPP pin was stressed three times at each HBM ESD level. Shift of I-V curve is the typical failure criterion used in the HBM ESD tests. Before ESD stress, a
25V voltage sweep with limited current supply was applied on VPP pin to acquire a fresh I-V
curve as the reference. Another post-stress I-V curve was measured and compared to this fresh I-V curve after the VPP pin had been stressed three times at each selected ESD test level.
It was judged as a failure when the post-stress I-V curve deviates more than 20% from its fresh I-V curve.
Fig. 6.11. TLP-measured I-V characteristics of the proposed ESD protection design under PS-mode ESD stress.
TABLE 6.2
MEASURED HBMESD ROBUSTNESS OF THE IC PRODUCT
WITH PREVIOUS ESD PROTECTION DESIGN OR THE PROPOSED ESD PROTECTION DESIGN AT VPP PIN.
With the PS- and PD-mode test results on VPP pin listed in Table 6.2, the substrate-triggered technique in collaboration with the N-Well ballast layout can successfully enhance the turn-on speed and turn-on uniformity of MN2. Therefore, HBM ESD protection
levels can be significantly increased up to 5 kV. For NS- and ND-mode ESD tests, because device dimension of the parasitic diode DMN2 is larger than that of the diode DN in the previous ESD protection design, the proposed ESD protection design showed a higher HBM ESD protection level of over 8 kV. From the measurement results shown in Table 6.2, the custom-specified 4-kV HBM ESD protection level has been successfully achieved by the proposed ESD protection design. Die photograph of the IC with the proposed ESD protection design is shown in Fig. 6.12, which has a die size of 3.72 mm2. The layout area of the proposed ESD protection circuit for VPP pin is 24186 m2, where MN2 occupies a silicon area of 15900 m2.
Fig. 6.12. Die photograph of the IC with proposed ESD protection design at VPP pin. Technology node used in this work is a 0.35-m fully-silicided CMOS process with OTP memory cells.
VPP pin with the proposed ESD protection design after 5.5-kV PD-mode HBM ESD test was analyzed by OBIRCH SEM, as shown in Fig. 6.13(a) and 6.13(b), respectively. OBIRCH analysis revealed the location of ESD damage on the ESD protection NMOS MN2. No light spots (no ESD damages) were found on internal circuits or the ESD trigger circuit. SEM
analysis further confirmed that ESD failure spots were located on MN2. These failure analyses have verified that the proposed ESD protection design at VPP pin is effective to protect internal circuits from being damaged by ESD stresses.
(a)
(b)
Fig. 6.13. (a) OBIRCH and (b) SEM images of the VPP pin with the proposed ESD protection design after 5.5-kV PD-mode HBM ESD stress.
6.5. Summary
Due to the high programming voltage on VPP pin, the ESD diode placed from I/O pad to VDD is prohibited, which results in a stringent ESD design challenge for VPP pin. Moreover,
the rise time of VPP programming voltage could be as fast as several tens of nanoseconds to cause mis-triggering issue in some traditional ESD protection designs. A new ESD protection design has been proposed to overcome the mis-triggering issue due to fast VPP programming voltage. A low-voltage NMOS was added at the output of ESD trigger circuit to overcome the mis-triggering issue on the ESD protection device during VPP programming. Moreover, ESD bus in the proposed design can help prevent the mis-triggering issue as well by reducing the overdrive current from ESD trigger circuit. The proposed ESD protection design has been successfully implemented on a commercial IC product fabricated in a 0.35-m fully-silicided CMOS process with OTP memory cells. Experimental results showed that the new design can successfully avoid the mis-triggering issue on ESD protection device when VPP voltage had a rise time as fast as 25 ns. Under ESD stress conditions, ESD protection device can be efficiently triggered on by substrate-triggered current to achieve a high HBM ESD protection level of 5 kV. Accordingly, with a high immunity against mis-triggering and a good ESD robustness, the new proposed design is a competent ESD protection solution to the CMOS IC products with high-voltage programming pin.
Chapter 7
Investigation on The Transistor Holding Voltage Acquired from TLP in a High-Voltage Technology
7.1. Background
Due to the high power supply voltage of HV ICs, latchup issue has become one of the most serious problems in HV applications, especially on the power-rail ESD protection devices [133]. Furthermore, HV ICs usually have high junction breakdown voltage and high gate oxide breakdown voltage, therefore the ESD design effort is focused on increasing the holding voltage (Vh) and minimizing the latchup sensitivity.
To analyze the device characteristics under ESD stresses, 100-ns TLP system has been widely adopted. TLP is a system which pre-charges the transmission line (T-line) through a high-voltage power supply and then discharges the pre-charged energy into the device under test (DUT). A TLP system generates a square wave to stress the DUT, and with gradually increased pre-charged voltages on T-line, a TLP system is capable of measuring the snapback I-V characteristics of devices. For example, the device trigger voltage (Vt1), holding voltage (Vh), secondary breakdown current (It2)…and so forth. Different from the 100-ns TLP system, a traditional curve tracer which sweeps a low-frequency voltage sine wave over the DUT can measure the snapback I-V characteristics, too. The frequency of the sine wave is low enough, so that the curve tracer measurement is considered as a DC measurement. Due to the long measurement duration, a curve tracer may damage the DUT especially under the snapback I-V measurement. Therefore, the holding voltages measured from the 100-ns TLP are sometimes regarded as reference data to latchup sensitivity in IC industry.
In this chapter, the holding voltages of an nLDMOS have been investigated by TLP systems with different pulse widths and the curve tracer. Transient latchup (TLU) test was
exploited to validate the measurement results.
7.2. Device Structure
The device cross-sectional view of an nLDMOS in a 0.25-m 18 V BCD process is shown in Fig. 7.1. The clearance from drain contact to poly gate edge, N+ extension from the drain contact, and the gate length Lch (poly gate overlap P-Drift) of the nLDMOS are optimized for ESD robustness. Gate and source electrodes of the nLDMOS are shorted together through internal metal wiring. The nLDMOS is laid out in finger type with each finger width of 50
m, and the total device width is 400 m.
Fig. 7.1. Device cross-sectional view of the nLDMOS in an 18 V BCD process.
7.3. Experimental Results and Discussion
The I-V characteristic of the nLDMOS under 100-ns TLP measurement is shown in Fig.
7.2(a) (squares). Steps of the T-line pre-charge voltage are 0.5 V, and I-V points are the averaged data from 50% to 90% of the pulse period. It2 of the nLDMOS is 1.5 A, and the corresponding HBM ESD robustness is higher than the general requirement of 2 kV. From the 100-ns TLP measurement, the nLDMOS shows a holding voltage of 11 V. However,
distinct from the results of low voltage devices, the holding voltage of nLDMOS under curve tracer measurement shows a substantial inconsistency to that measured by 100-ns TLP. As shown in Fig. 7.2(b), the holding voltage of nLDMOS under curve tracer measurement is 5.7 V only.
(a)
(b)
Fig. 7.2. I-V characteristics of the nLDMOS measured by (a) 100-ns and 1000-ns TLP, and (b) a DC curve tracer.
To investigate the huge Vh roll off from 100-ns TLP (11 V) to curve tracer (5.7 V), long-pulse TLP system with 1000-ns pulse width [134] was exploited. The long-pulse TLP
system is capable of providing pulse widths longer than100ns, so that the time-domain device behavior of HV devices after 100ns can be further observed. As the measured result shown in Fig. 7.2(a) (solid triangles), nLDMOS under 1000-ns TLP has Vh of 9.1 V, which is lower than the Vh under 100-ns TLP measurement but higher than the Vh under curve tracer measurement. The corresponding time-domain current and voltage waveforms of 1000-ns TLP measurement are shown in Fig. 7.3, where perceptible degradation over time is observed.
Fig. 7.3. Time-domain waveforms of the nLDMOS under 1000-ns long-pulse TLP measurement.
From the Wunsch-Bell model, the simplified temperature model T(0, ) under the power source of a rectangular pulse with duration is (0, ) q0
T t
D
(t ) [135]. As a result, device temperature increases with time (t ) during the duration of TLP pulses ( ). In HV devices, the high device holding voltages can further accelerate the self-heating effect.
With the increasing device temperature over time, -gain of the parasitic bipolar inherent in nLDMOS also increases. The holding voltage of nLDMOS therefore degrades while the time increases, as the waveform shown in Fig. 7.3. Extrapolating the measured voltage waveform in Fig. 7.3, time for the nLDMOS to reach Vh of 5.7 V is estimated as 3.2 s.
Fig. 7.4. Time-domain voltage waveform of the nLDMOS under transient latchup measurement with initial positive Vcharge of +30V.
Transient latchup test has been verified as an effective test method to evaluate the susceptibility of CMOS ICs to the latchup induced by transient noises in field applications [136]–[138]. The test setup for TLU is shown in the inset of Fig. 7.4. In the TLU test, the nLDMOS was initially biased at normal circuit operating voltage of 18 V. A transient noise is injected into nLDMOS from the transient trigger source with pre-charged voltage Vcharge of +30 V. After the transient triggering, the nLDMOS was driven into latchup state and clamped down the supply voltage. From the measured voltage waveform of TLU test in Fig. 7.4, the nLDMOS clamped the supply voltage to ~5.7 V, which is the same value of Vh under curve-tracer measurement. Moreover, time for nLDMOS to clamp the supply voltage into a steady state is roughly around 1000 ns, whereas the voltage at 1000 ns under 1000-ns TLP measurement in Fig. 7.3 is ~9 V. In consequence, the TLU test has verified that the TLP system overestimates the holding voltage of a HV device, which, in turn, could underestimate its susceptibility to latchup.
7.4. Summary
The holding voltage of an nLDMOS in a HV BCD process has been investigated by TLP measurements with different pulse widths and DC curve tracer. It is found that the holding voltages of an 18-V nLDMOS measured by 100-ns TLP system and curve tracer are substantially different, 11 and 5.7 V , respectively. The self-heating effect which degrades the holding voltage of nLDMOS over time has been observed. By using the long-pulse TLP, the self-heating speed of the HV transistors can be quantitatively estimated. TLU test further verifies that TLP systems overestimate the holding voltage of nLDMOS and underestimate its susceptibility to latchup. As a result, TLP measurement is not suitable for investigating the holding voltage of HV devices, especially for the latchup development because latchup events have the time duration longer than a millisecond.
Chapter 8
Conclusions and Future Works
This chapter summarizes main results of this dissertation and from the research results some suggestions and future works are proposed.
8.1. Main Results of This Dissertation
After a brief ESD introduction in Chapter 1, a waffle layout method that utilizes the body-current injection on the nLDMOS is proposed in Chapter 2. Through TLP and ESD measurements and failure analyzes, experimental results show that this proposed method is able to substantially improve turn-on uniformity of nLDMOS transistors in a 0.5-m 16-V and a 0.35-m 24-V BCD process. This waffle layout structure is suitable for I/O or power-rail ESD clamp circuit.
For open-drain structures, integrating SCR into output nLDMOS is a common ESD solution. However, the safe operating area, as one of the important reliability indicators of output arrays, is degraded due to the embedded SCR. In Chapter 3, SOA is reviewed along with some up-to-date technologies on improving SOA of HV transistors. Following the SOA review in Chapter 3, a poly bending method that alleviates the degradation on SOA performance but keeps the high ESD robustness from SCR is proposed in Chapter 4. With the poly bending layout method, a HV output array that has both high ESD robustness and wide SOA is available for HV ICs. Combining the results in Chapter 2 and 4, the two methods can provide excellent ESD robustness to HV ICs with either traditional or open-drain structures.
With ESD being a practical reliability requirement of ICs, two ESD designs for fully-silicided technologies are included in Chapter 5 and Chapter 6. In Chapter 5, two novel ballasting techniques are proposed. The proposed methods ballast not only the output NMOS,
but also the output PMOS transistor to maximize the ESD robustness. From measurement results on a real IC product, the two ballasting method effectively equipped the IC with at least 6 kV HBM ESD robustness.
In chapter 6, a fully-silicided ESD protection design for voltage programming pins is proposed. The proposed design features both high ESD protection level and high immunity against mis-triggering when the input voltage has a rise time similar to ESD events, tens of nanoseconds. A commercial IC equipped with this ESD protection circuit passed 5-kV HBM ESD robustness. Finally, in Chapter 7, a new phenomenon of HV transistors’ holding voltage in response to stress time is investigated by using TLP systems with different pulse widths.
Results in Chapter 7 are useful for the future development of high-latchup-immunity transistors or ICs in HV technologies.
8.2. Future works
For the operation of power MOSFETs, it is very often that the transistors’ drain or ground potentials be perturbed greatly, especially when switching with a large current. Noise immunity of the nLDMOS transistors and the impact that comes from the SCR insertion is an important future work thereof. A challenge to this study would be the fact that noises from different systems or applications are case-sensitive, and presently there is no unified standard or platform suitable for device-level measurements. Testing ICs on their system boards is necessary for this noise study on power MOSFETs.
The VPP pin ESD protection design in Chapter 6 has the lowest potential of 0 V because of its application specifications. For ICs with their lowest voltage potentials below 0 V, e.g.
NAND memories, the ESD protection design along with its trigger circuit should be modified and it would be both interesting and useful to implement such an application-oriented ESD protection design.
With the high power supply voltages in HV applications, latchup is an extremely challenging reliability topic. Designing a structure with high latchup immunity has been an important development target in HV ICs for decades. From the research results in Chapter 7, the challenge becomes more stringent and correct measurement techniques to evaluate the latchup immunity of HV transistors are equally important. With the new observed phenomenon, latchup in HV ICs will face new challenges; new physical mechanisms to be discovered as well. Accordingly, latchup is a topic not only intriguing but also valuable to the IC industries, and worthy to put further efforts for future works and developments.
References
[1] B. Baliga, Advanced Power MOSFET Concepts. Springer, 2010.
[2] A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits. John Wiley & Sons, 2002.
[3] Electrostatic Discharge (ESD) Sensitivity Testing―Human Body Model (HBM), EIA/JEDEC Standard Test Method 5.1, 2001.
[4] Electrostatic Discharge (ESD) Sensitivity Testing―Machine Model (MM), EIA/JEDEC Standard Test Method 5.2, 1999.
[5] Field-Induced Charged-Device Model Test Method for Electrostatic Discharge Withstand Thresholds of Microelectronic Components, JESD22-C101C, 2004.
[6] M.-D. Ker, “Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuit for submicron CMOS VLSI,” IEEE Trans. Electron Devices, vol. 46, no. 1, pp.
173–183, 1999.
[7] B. Keppens, M. Mergens, C. Trinh, C. Russ, B. Camp, and K. Verhaege, “ESD protection solutions for high voltage technologies,” in Proc. EOS/ESD Symp., 2004, pp.
289–298.
[8] P. Wessels, M. Swanenberg, H. Zwol, B. Krabbenborg, H. Boezen, M. Berkhout, and A.
Grakist, “Advanced BCD technology for automotive, audio and power applications,”
Solid-State Electronics, vol. 51, no. 2, pp. 195–211, 2007.
[9] S.-H. Chen and M.-D. Ker, “Area-efficient ESD-transient detection circuit with smaller capacitance for on-chip power-rail ESD protection in CMOS ICs,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 5, pp. 359–363, 2009.
[10] M.-D. Ker, W.-Y. Chen, and K.-C. Hsu, “Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS
process,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 10, pp. 2187–2193, 2006.
[11] M.-D. Ker and K.-H. Lin, “Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations,” IEEE Trans.
Circuits Syst. I, Reg. Papers, vol. 53, no. 2, pp. 235–246, 2006.
[12] M.-D. Ker and H.-C. Hsu, “ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 1, pp.
44–53, 2005.
[13] M. Mergens, W. Wilkening, S. Mettler, H. Wolf, A. Stricker, and W. Fichtner, “Analysis of lateral DMOS power devices under ESD stress conditions,” IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2128–2137, 2000.
[14] M.-D. Ker and W.-J. Chang, “On-chip ESD protection design for automotive vacuum-fluorescent-display (VFD) driver IC to sustain high ESD stress,” IEEE Trans.
Device and Mater. Reliab., vol. 7, no. 3, pp. 438–445, 2007.
[15] G. Boselli, V. Vassilev, and C. Duvvury, “Drain extended nMOS high current behavior and ESD protection strategy for HV applications in sub-100nm CMOS technologies,” in Proc. IEEE Int. Reliab. Phys. Symp., 2007, pp. 342–347.
[16] J.-H. Lee, S.-H. Chen, Y.-T. Tsai, D.-B. Lee, F.-H. Chen, W.-C. Liu, C.-M. Chung, S.-L.
Hsu, J.-R. Shih, A.-Y. Liang, and K. Wu, “The influence of NBL layout and LOCOS space on component ESD and system level ESD for HV-LDMOS,” in Proc. Int. Symp.
Power Semiconductor Devices and ICs, 2007, pp. 173–176.
[17] V. Parthasarathy, V. Khemka, R. Zhu, J. Whitfield, A. Bose, and R. Ida, “A double RESURF LDMOS with drain profile engineering for improved ESD robustness,” IEEE Electron Device Lett., vol. 23, no. 4, pp. 212–214, 2002.
[18] Y.-J. Seo and K.-H. Kim, “Effects of background doping concentration on electrostatic discharge protection of high voltage operating extended drain N-type MOS device,”
Microelectronic Engineering, vol. 84, no. 1, pp. 161–164, 2004.
[19] K.-H. Kim and W.-J. Choi, “Effects of background doping concentration on ESD protection properties of high-voltage operation extended drain N-type MOSFET device,”
in Proc. IEEE Int. Reliab. Phys. Symp., 2007, pp. 334–341.
[20] K. Kawamoto, S. Takahashi, S. Fujino, and I. Shirakawa, “A no-snapback LDMOSFET with automotive ESD endurance,” IEEE Trans. Electron Devices, vol. 49, no. 11, pp.
2047–2053, 2002.
[21] W.-Y. Chen and M.-D. Ker, “High-voltage nLDMOS in waffle-layout style with body-injected technique for ESD protection,” IEEE Electron Device Lett., vol. 30, no. 4, pp. 389–391, 2009.
[22] W.-Y. Chen, M.-D. Ker, Y.-N. Jou, Y.-J. Huang, and G.-L. Lin, “Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection,” in Proc. IEEE Int. Symp. Circuits and Systems, 2009, pp. 385–388.
[23] A. W. Ludikhuize, “A review of RESURF technology,” in Proc. Int. Symp. Power Semiconductor Devices and ICs, 2000, pp. 11–18.
[24] T. Maloney and N. Khurana, “Transmission line pulsing techniques for circuit modeling of ESD phenomena,” in Proc. EOS/ESD Symp., 1985, pp. 49–54.
[25] G. Notermans, O. Quittard, A. Heringa, Ž. Mrčarica, F. Blanc, H. Zwol, T. Smedes, T.
Keller, and P. Jong, “Designing HV active clamps for HBM Robustness,” in Proc.
EOS/ESD Symp., 2007, pp. 47–52.
[26] T.-Y. Chen and M.-D. Ker, “Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices,” IEEE Trans. Device and Mater. Reliab., vol. 1, no. 4, pp. 190–203, 2001.
[26] T.-Y. Chen and M.-D. Ker, “Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices,” IEEE Trans. Device and Mater. Reliab., vol. 1, no. 4, pp. 190–203, 2001.