SCR-nLDMOS and D P width to eSOA (Gate SCR internally short circuited to

With the SCR embedded in an nLDMOS array (SCR-nLDMOS), parasitic devices become more complicated than that of nLDMOS without embedded SCR. Equivalent circuit of the embedded SCR is shown in Fig. 4.4. The equivalent circuit in Fig. 4.4 resembles an insulated gate bipolar transistor (IGBT) [76], except for the RN connecting emitter and base of PNP BJT. The RN resistor comes from the N+ regions next to DP, i.e. R1 and R2 in parallel as shown in Fig. 4.2(b). Therefore, SCR-nLDMOS with a smaller DP width has a smaller equivalent RN.

Fig. 4.4. The equivalent circuit of the embedded SCR in the nLDMOS arrays.

It should be noted that in a high voltage technology where IGBT is a dedicated power device, the regenerative feedback of parasitic SCR in the IGBT is suppressed carefully to avoid latch up under normal circuit operating conditions [77]–[79]. However, for HV technologies with relatively low voltage ratings (typically < 200 V processes, so that the studied process is included, too), IGBT usually is not a dedicated device and SCR is used for ESD protection purposes. SCR structures in these technologies are made up of parasitic BJTs without being specially suppressed during process development. As a result, the sum of open-base current gains of parasitic PNP (PNP) and NPN (NPN) BJTs in these technologies can be higher than 1 to initiate regenerative feedback even under normal circuit operating conditions [80].

Measured TLP I-V curves of SCR-nLDMOS without and with PBI layer are shown in Fig.

4.5(a) and 4.5(b), respectively. Gate bias for DUTs in Fig. 4.5 was 0 V, and leakage currents were measured under the drain bias of 24 V. In Fig. 4.5(a), both SCR-nLDMOS with DP of 10 and 50 m can sustain 100-ns TLP stresses higher than the limitation of the TLP system used, 3.75A. For SCR-nLDMOS with DP of 5 m, because a smaller DP width results in a smaller RN resistor, emitter-base junction of PNP BJT becomes harder to be forward biased. As a result, DP of 5 m in Fig. 4.5(a) exhibits the highest measured trigger voltage (Vt1) of 48.62 V.

Measured Vt1 for nLDMOS without PBI in Fig. 4.3 is 49.04 V. These two measured Vt1

values of 48.62 and 49.04 V show that when DP is as small as 5 m, trigger competition can easily happen between the 4 fingers with embedded SCR (GateSCR fingers) and the other 44 fingers without embedded SCR (GateMOS fingers). As a result, instead of showing a high TLP-measured It2, SCR-nLDMOS with DP of 5 m failed (leakage current increased over 10X) at 1.31 A in Fig. 4.5(a). Because the failure arises from trigger competition between GateSCR and GateMOS fingers, a virtual zero ESD protection level on SCR-nLDMOS without PBI under DP of 5 m is possible.

(a)

(b)

Fig. 4.5. Measured TLP I-V characteristics of SCR-nLDMOS (a) without PBI and (b) with PBI.

Gate bias for all DUTs was 0 V and leakage currents were measured under 24-V drain bias.

For SCR-nLDMOS with PBI, because the measured Vt1 for gate-grounded nLDMOS with PBI in Fig. 4.3 is increased to 58.47 V, trigger competition between GateSCR and GateMOS

fingers is averted. All DUTs in Fig. 4.5(b) therefore have It2 higher than the equipment limitation of 3.75 A. Effectiveness on embedded SCR to improve ESD robustness therefore has been verified through measurement results in Fig. 4.5.

Fig. 4.6. Measured eSOA of SCR-nLDMOS with Gate_SCR short circuited to Gate_MOS. The corresponding gate biases for the IDS from low to high were 0, 3, 6, 9, 12, and 16 V, respectively.

Some measured DUTs have less than 6 data points because these DUTs under high gate biases were driven directly into SCR operation without manifesting distinct snapback to determine their eSOA boundaries.

When the potential of GateSCR is pulled high to induce channel current, electrons are provided from the N+ source (IG) and holes emitting from P+ anode of SCR can be recombined with these electrons. This is shown as J1 current flow in Fig. 4.2(b). However, instead of being recombined with electrons, part of the emitting holes from P+ anode is drawn to the vicinity of channel due to the negative charge of electrons and then be swept to the grounded P+ body contacts through the P-body/PBI (J2 current flow in Fig. 4.2(b)). These holes traveling through P-body/PBI develop a voltage drop across the base-emitter junction of NPN BJT, which will eventually trigger on NPN BJT and lead to positive regenerative feedback of SCR during normal circuit operating conditions. This can also be understood from the equivalent circuit shown in Fig. 4.4 where the IG current serves as the base current of PNP BJT and further induces the IC1 collector current [81]. Once the base-emitter junction

of NPN BJT in Fig. 4.4 is forward biased, SCR is triggered on and latchup happens.

Measured eSOA for SCR-nLDMOS without and with PBI layer are shown in Fig. 4.6.

DUTs in Fig. 4.6 have GateSCR internally connected to GateMOS, so that when a positive gate bias is applied to DUTs in Fig. 4.6, GateSCR potential is pulled high along with GateMOS

potential. Comparing eSOA shown in Fig. 4.3 and 4.6, a substantially narrowed eSOA due to embedded SCR is observed. This means by inserting SCR into nLDMOS arrays for ESD protection, the SOA boundary is changed from the triggering of NPN BJT to the triggering of SCR due to the strong positive regenerative feedback of the P-N-P-N structure.

Comparing measurement results in Fig. 4.6 with the same DP width, SCR-nLDMOS with PBI layer constantly shows a better eSOA performance than that of SCR-nLDMOS without PBI layer. This is due to the fact that PBI layer not only suppresses bipolar beta gain of NPN BJT (NPN), but also makes base-emitter junction of NPN BJT harder to be forward biased.

Measurement results in Fig. 4.6 also reveal a strong dependency of eSOA to DP width. Under the same gate and anode voltages, a smaller RN (shorter DP) helps keep the node A voltage in Fig. 4.4 at a relatively higher potential. This diminishes the emitting holes from P+ SCR anode by reducing the voltage difference across the emitter-base junction of PNP BJT. With the number of holes emitting from P+ anode being suppressed, J2 current in Fig. 4.2(b) to forward bias the base-emitter junction of NPN BJT is reduced as well. Accordingly, SCR-nLDMOS with a shorter DP width showed a better eSOA performance in Fig. 4.6.

However, combining the information from Fig. 4.5(a) and 4.6, though reducing DP width when embedding SCR to nLDMOS array is beneficial to eSOA, there is a limitation on the smallest applicable DP width which comes from the condition of trigger competition between GateSCR and GateMOS fingers.

(a)

(b)

Fig. 4.7. Measured voltage waveforms when switching a 50- resistive load under 24-V power supply voltage and a 0-to-6 V voltage pulse on gate. DUTs are (a) nLDMOS without embedded SCR and (b) SCR-nLDMOS with D_P of 50 µm. Both measured DUTs do not have the PBI layer. Gate_SCR in the measured SCR-nLDMOS is short circuited to GateMOS.

Importance of the substantially narrowed SOA to the device reliability for circuit operation is shown in Fig. 4.7(a) and 4.7(b). In Fig. 4.7(a), an nLDMOS (without PBI) was used to drive a 50- resistive load, which is common in analog circuit applications. As the measurement setup shown in the inset of Fig. 4.7(a), the 50- resistor was biased at 24 V, and a 0-to-6 V VGS pulse was applied to turn on and turn off the DUT. Measured VDS and VGS

waveforms in Fig. 4.7(a) show that the nLDMOS without PBI can safely drive the 50

resistive load. However, when doing the same 50- resistive load test on SCR-nLDMOS with DP of 50 m (without PBI), DUT was burned out after the measurement. As the measurement results shown in Fig. 4.7(b), measured VDS drops to the holding voltage of the embedded SCR (~2 V) when the DUT starts to conducting current. SCR is triggered on during the circuit switching, so that the latchup-like failure happens, and the DUT can no longer be controlled by the gate bias. Accordingly, though inserting SCR to nLDMOS has been proven to substantially increase ESD robustness, the degraded SOA should be carefully examined to avoid device failure under normal circuit operating conditions.