Summary

nLDMOS transistors in HV technologies are known to have poor ESD robustness.

Additional P-type boron implantation was found to degrade ESD robustness of snapback-based nLDMOS. Through the collaboration of the proposed waffle layout style and the ESD trigger circuit, the body-injected technique was fulfilled in a 0.5-m 16-V and a 0.35-m 24-V BCD process. The 100-ns TLP measurement results showed substantially improved It2 on waffle nLDMOS. Failure analyses further revealed improvement on the turn-on uniformity of nLDMOS by the body current injection. From these experimental results, the body-injected technique is effective in increasing the ESD robustness of nLDMOS.

Chapter 3

Overview to The SOA Characterization and Improvement Techniques in Power MOSFETs

3.1. Background

High voltage and high current operations are common environments for power semiconductor devices. To sustain the high VCC operating voltage, sufficient breakdown voltage (BVDSS) is a must for power semiconductors. To minimize the power consumption over a switching transistor, device turn-on resistance per unit area, i.e. the specific on-resistance RSP, is another important factor for the development of power devices. Safe operating area (SOA), as the third factor to meet the HV and high current requirements, defines the voltage-current boundary in which a power transistor can safely switch. The three factors, BVDSS, RSP, and SOA, are therefore known as the design triangle of power semiconductor devices as shown in Fig. 3.1 [32].

Fig. 3.1. The design triangle of power semiconductor devices (redrawn after [32]).

3.2. Physical Limitation of SOA

The physical limitation of SOA in a power MOSFET lies in the triggering of intrinsic BJTs [33]. The equivalent circuit model of a HV NMOS is shown in Fig. 3.2. RD, RS, and RB are respectively (parasitic) drain, source, and body resistors of the HV NMOS; Ih is the hole

current that can forward bias the bipolar base-emitter junction through RB and trigger on the intrinsic NPN BJT. Major sources of the current Ih include avalanche-generated holes (IAV) and thermal generation (ITG) due to device self-heating, which can be expressed as

. (3.1)

Fig. 3.2. The equivalent circuit model of a HV NMOS. Parasitic BJT and resistors are included.

Fig. 3.3. The test setup of eSOA measurement with 100-ns TLP.

From equation (3.1), IAV is a result of impact ionization, so that it is a function of both the drain-source current IDS and avalanche multiplication factor M [33]. To minimize the effect of device self-heating and to estimate the impact to SOA that comes from IAV, DUTs are usually

stressed by pulses with a short pulse width. Such an electrical SOA (eSOA) boundary is important when thermal effect is not strongly involved during operation; small devices that benefit from good lateral thermal spreading, for example [32]. A 50- TLP system that delivers square pulses with an 100-ns pulse width is usually adopted for the measurement of eSOA [24], [32]. The setup of eSOA measurement is shown in Fig. 3.3, and measured eSOA boundaries of two 24-V nLDMOS are shown in Fig. 3.4. Because snapback (triggering of the intrinsic BJT) usually causes irreversible damage to a power MOSFET or induces circuit malfunctions, the eSOA boundary is defined by sweeping different gate biases and connecting the I-V points right before the device snapback. A higher gate bias causes a reduction in VDS rating because a higher IDS accelerates the number of electron-hole pairs generated from impact ionization (higher IAV).

Fig. 3.4. Measured eSOA boundaries of two nLDMOS transistors.

When a power MOSFET operates with strong device self-heating, ITG in equation (3.1) can become the dominating factor to cause device failure. The intrinsic doping concentration (ni) in a semiconductor device is a strong function of temperature [34]

^⁄ , (3.2)

where K is the Boltzmann constant, T is the temperature, EG is the energy bandgap, and NC

and NV are the effective electron and hole density of states, respectively. From equation (3.2), extrinsic doping concentration is overwhelmed by ni under high temperatures and the device become intrinsic semiconductor. Thermal SOA (tSOA) defines the boundary of device failure initiated by thermal instability [32], [35]. Tendencies of eSOA and tSOA boundaries with respect to temperature and pulse widths are depicted in Fig. 3.5 [32], [36]. When temperature increases, usually the eSOA shifts downward. A longer pulse width induces a stronger device self-heating, and the tSOA shifts inward. At a certain pulse width the tSOA boundary becomes enclosed within the eSOA. The tSOA is accordingly important for a large-area power MOSFET that has severe thermal accumulation, or when a power MOSFET is operated with a long (~ms) pulse time, solenoid drivers for example.

Fig. 3.5. A diagram showing tendencies of eSOA and tSOA with respect to temperature and pulse widths.

Though eSOA and tSOA define boundaries from different mechanisms, the two effects are usually coupled in nature as an electrothermal effect [36], [37]. RD, RS, and RB resistors in the equivalent circuit model have positive temperature coefficients. The increases in RD and RS

resistances under high temperature can suppress IAV due to a reduced IDS. The increases in RB

resistance, on the contrary, help forward bias the base emitter junction and make the parasitic BJT easier to be triggered on. Avalanche multiplication factor M and the built-in potential of a bipolar base-emitter junction are also functions of temperature [32]. Techniques to decouple the electrical and thermal effects through deactivating the parasitic BJT showed an appreciable electrothermal coupling to determine the SOA of power MOSFETs [38], [39]. It is therefore hard to acquire pure electrical or thermal SOA under different gate biases, and the SOA chart of a power MOSFET usually has boundaries under different pulse widths. Fig. 3.6 is an example showing different regions of SOA for a power MSOFET. There are four regions in Fig. 3.6; region (A) is limited by the turn on resistance RDS,ON of the power MOSFET. Region (B) is limited by the current carrying capability either from the power MOSFET or the package. Region (C) is determined by the operating current and voltage across the power MOSFET (power limited). When pulse width increases, region (C) moves downward due to the increasing device self-heating and the electrothermal coupling. Region (D) is defined by the maximum drain to source voltage rating, the BVDSS. In Fig. 3.6, because boundaries are defined when turning the power transistor into on-state, it is referred to as the forward-biased SOA (FB-SOA).

Fig. 3.6. A Diagram showing FB-SOA of a power MOSFET.

Fig. 3.7. Test circuit of an nLDMOS switching an external capacitor. C_EXT with different capacitances were used in this test.

3.3. Switching Reactive Loads

Power transistors are used to drive various loads in industrial and automotive applications.

A switching trajectory within the SOA boundary ensures safe operation of a power transistor.

A wide SOA boundary is therefore preferred so as to enhance device reliability under various operating conditions. It is equally important to understand the I-V loci when switching different loads.

3.3.1. Capacitive Load

For a resistive load, the switching loci are relatively simple and follow the Ohm’s law.

However, when switching a reactive load, the switching loci become complicated. Voltage and current can have phase differences, resulting in high voltage and high current to occur at the same time. Test circuit of an nLDMOS to drive a large external discrete capacitor, output of a gate driver IC for example, is shown in Fig. 3.7. Capacitances used in the test circuits were 2.7, 4.7, and 10 nF. When the nLDMOS is switched on, CEXT is charged up through the IDS current of the nLDMOS. However, due to the RC time delay from the resistances of nLDMOS and metal wiring, and the capacitance of CEXT, source voltage (VS) of the

nLDMOS is not pulled high immediately. Measured I-V waveforms in Fig. 3.8(a) clearly show the high VDS and high IDS to happen at the same time. The IDS current in Fig. 3.8 is acquired from a current probe; the VDS voltage is calculated from (VCC – VS); VS is measured by using a voltage probe. When CEXT is increased, a larger RC time delay causes a larger and a longer IDS-VDS stress across the nLDMOS. The I-V switching trajectories in Fig. 3.8(a) are redrawn in Fig. 3.8(b). Waveforms in Fig. 3.8(a) also suggest that when switching a capacitive load, eSOA is important due to the relatively short I-V stress time across the switching transistor [32].

(a)

(b)

Fig. 3.8. Measured (a) turn-on waveforms and (b) I-V trajectories of an nLDMOS switching capacitors with different capacitance values.

3.3.2. Inductive Load (Unclamped Inductive Switching)

Another typical example is the switching trajectory for inductive turn-off. Application example includes the solenoid driver or the relay actuator. The test circuit and some parameters used are shown in Fig. 3.9. Without additional clamping element in parallel to the inductor, this test is usually referred to as the unclamped inductive switching (UIS) and is important for stringent operating environments such as automotive electronics [40]–[42].

When the nLDMOS is turned on, the current increasing rate follows the relationship

, (3.3) where the total series resistance along the circuit is assumed to be small. As the measured I-V waveforms shown in Fig. 3.10(a), within the turn-on period TPW (pulse width of the gate signal VGS) the measured IS current linearly increases with time and the VDS has a voltage level close to the ground. During the turn-on stage, the total energy stored in the inductor is given by

. (3.4) IAS is the load current right before switching off the nLDMOS; IAS in Fig. 3.10(a) is ~110mA for example.

Fig. 3.9. Test circuit for unclamped inductive switching of an nLDMOS.

(a) (b)

(c) (d)

Fig. 3.10. Measured UIS waveforms with different LEXT, VCC, or TPW parameters. (a) LEXT = 220 H, V_CC = 24 V, T_PW = 1 s, (b) L_EXT = 220 H, V_CC = 12 V, T_PW = 1 s, (c) L_EXT = 220 H, V_CC = 24 V, TPW = 2 s, and (d) LEXT = 1 mH, VCC = 24 V, TPW = 4.45 s.

When the nLDMOS is switched off, the current flowing through the inductor cannot immediately drop to zero. The energy stored in the inductor drives up the VDS voltage of the nLDMOS and forces the nLDMOS to discharge the load energy through avalanche breakdown [43]–[45]. The peak current IAS corresponds to the avalanche current, and the energy EAS to be dissipated during inductive turn-off is

. (3.5) As the measured waveforms shown in Fig. 3.10(a), when the VGS is turned off, the VDS

voltage shoots up to the breakdown voltage (BV) of the nLDMOS (~58 V); current begins to decrease linearly and the VDS voltage is kept high until IS drops to zero. The current decreasing rate during inductive turn-off follows

. (3.6)

Since the switching transistor is operated under avalanche breakdown, the time to discharge the energy stored in the inductor is usually referred to as tAV. From equation (3.6), tAV can be derived as [45]

. (3.7) With the above equations, several parameters affecting the UIS waveforms can be observed from Fig. 3.10. When VCC voltage is reduced from 24 to 12 V, equations (3.3) and (3.7) suggest that IAV should be reduced to a half and tAV is shortened as well (Fig. 3.10(a) and 3.10(b)). The voltage oscillation after tAV is due to the LC oscillation of the LEXT and the parasitic capacitance of the voltage probe. Increasing the TPW width from 1 to 2 s doubles IAV; tAV increases as well (Fig. 3.10(a) and 3.10(c)). When the inductance is increased from 220 H to 1mH, TPW is increased from 1 to 4.45 s to reach the same IAV current (Fig. 3.10(a) and 3.10(d)). From equations (3.5) and (3.7), at the same IAV the larger inductance results in a longer t_AV and a larger energy to be dissipated, i.e. the transistor is stressed more severely.

From Fig. 3.10(a) and 3.10(c), dependence between the peak VDS voltage and the IAV

magnitude during inductive turn-off, though weak, is also observed. For a gate-grounded nLDMOS entering avalanche breakdown, the I-V characteristic is illustrated as Fig. 3.11.

When the VDS voltage across an nLDMOS is higher than its BVDSS, avalanche current IAV

starts to flow; snapback does not happen immediately until the current magnitude reaches It1, at which the BJT base-emitter junction is forward biased through RB (Fig. 3.2). The IAS

current level during UIS test cannot exceed It1, otherwise the nLDMOS snaps back and a latchup-like electrical overstress (EOS) will permanently damage the nLDMOS. For an UIS

test with a peak inductor current IAS1, the energy stored in the inductor will correspondingly charge up the drain voltage to VDS1 during inductive turn-off so as to keep the current continuity. From Fig. 3.11, it is known that a higher peak inductor current IAV2 causes a higher voltage VDS2 during inductive turn-off. Note that ITG in equation (3.1) can contribute greatly to the device snapback in UIS because of the high power during avalanche breakdown and the long tAV during inductive turn-off (from several s up to several tens of ms) [46].

Fig. 3.11. A diagram depicting the I-V characteristic of a gate-grounded nLDMOS.

Because the stress across the transistor in an UIS test happens during transistor turnoff, it is classified as the reverse-biased SOA (RB-SOA) and usually has different rating methods than the FB-SOA. The term RB-SOA is often reserved for BJTs switching unclamped inductive load, and for MOSFETs UIS is used more often. To evaluate the transistor ruggedness against UIS, two parameters are usually adopted as the benchmark. The first parameter is the maximum allowable switching current (IAS,Max) without inducing transistor failure [40], [47].

The other rating method uses the maximum energy EAS,Max dissipated in the switching transistor without inducing failure as the benchmark. The second method is usually referred to as the energy capability of a power MOSFET [41].

3.3.3. Inductive Load (Clamped Inductive Switching)

Due to the high junction temperature over a MOSFET during avalanche breakdown, UIS is a harsh test for power MOSFETs. In practical designs, the clamped inductive switching (CIS) is usually used to bypass the energy during inductive turn-off without avalanching the switching transistor.

Fig. 3.12. A CIS test circuit using a zener diode to clamp the nLDMOS drain voltage during inductive turnoff.

Fig. 3.13. Measured I-V waveforms of the CIS test circuit. The breakdown voltage of the zener diode is 37 V.

An example of the CIS circuit is shown in Fig. 3.12 [38], [48]. When switching off the inductive load, the zener diode D1 breaks down and a current IZ pulls high the gate potential of the nLDMOS through the diode D2 and the R1 resistor. The D1 diode is chosen to have a breakdown voltage BVZ smaller than the BVDSS of the nLDMOS so as to prevent nLDMOS from avalanche breakdown. The drain voltage of the nLDMOS during inductive turn-off is therefore limited at . With the gate potential pulled high, the energy stored in the inductor is mainly discharged through the channel current of the nLDMOS. Measured I-V waveforms of the zener-clamped CIS circuit are shown in Fig. 3.13;

BVZ of the D1 in Fig. 3.13 is 37 V, and the nLDMOS is the same transistor used to measure Fig. 3.10. When switching off the inductor, the measured VDS voltage is clearly limited at a lower voltage level around 40 V. Note that in CIS, FB-SOA of the switching transistor is important as well because the transistor has to sustain Vclamp and the inductive turn-off current at the same time.

In the zener-clamped CIS circuit, because the drain voltage of the nLDMOS is limited at Vclamp, the time toff to dissipate the energy stored in the inductor becomes

, (3.8) where IMAX is the current right before switching off the nLDMOS. Comparing equations (3.7) and (3.8), with the Vclamp smaller than the breakdown voltage of nLDMOS, the zener-clamped CIS results in a longer inductive turn-off time as shown in Fig. 3.13. The energy dissipated in the nLDMOS during the turn-off period becomes

. (3.9)

When measuring energy capabilities, equations (3.5) and (3.9) show that different inductances, current magnitudes, zener diodes…etc have to be changed during tests to figure out the EAS,MAX of a DUT. It is, however, inconvenient and difficult to control. To facilitate the measurement, alternative rectangular power pulsing (RPP) test methods which use

rectangular voltage or current pulses with different pulse widths have been proposed [48].

Voltage and current RPP testing circuits are shown in Fig. 3.14(a) and 3.14(b), respectively.

The RPP tests save the usage of external inductors. Energy capabilities of DUTs can be easily figured out simply by varying the pulse width or the magnitude of delivered voltage / current pulses. Though in a real inductive switching condition the current waveform is in a triangular shape, RPP tests have been verified to deliver reasonably accurate results [48].

(a) (b)

Fig. 3.14. Measurement setups for (a) voltage and (b) current rectangular power pulsing test circuits (redrawn after [48]).

3.4. Techniques to SOA Improvement

Aside from the CIS method to assist transistors, techniques to improve the intrinsic SOA of power MOSFETs are always preferred. This section introduces the SOA improvement techniques that have been reported.

3.4.1. Additional Body Implantation

Since the criterion for a BJT to be triggered on is the forward conduction of its base-emitter junction, reducing the parasitic RB resistor in Fig. 3.2 is effective in widening the MOSFET SOA [49]–[51]. The process integration method in reducing the RB resistor is illustrated in Fig. 3.15. Comparing to the regular nLDMOS structure shown in Fig. 3.15(a),

an additional P-type body implantation is added to elevate the doping concentration of P-body (see Fig. 3.15(b)). Measured eSOA of the regular nLDMOS is the boundary (A) in Fig. 3.4; nLDMOS with the additional P-type implantation at body has the eSOA boundary (B) in Fig. 3.4. Both devices have the same effective width of 4800 m. It is clear from Fig.

3.4 that the additional P-type body implantation substantial improves the FB-SOA of power MOSFETs. With the reduced RB, IAS,MAX in an UIS test for the 4800-m nLDMOS improves from 100 to 350 mA as well, a result consistent to previous publications [49], [50].

(a)

(b)

Fig. 3.15. Device cross-sections of (a) a regular nLDMOS and (b) an nLDMOS with additional P-type implantation at body to improve SOA.

(a) (b)

Fig. 3.16. Layout and device cross-sectional views of (a) a regular LDMOS and (b) a dotted-channel LDMOS for SOA improvement (redrawn after [52]).

3.4.2. Dotted Channel LDMOS

An approach to reducing the RB resistance and suppressing the BJT action through process integration is useful, but often inaccessible to fabless IC design companies. A layout technique for the SOA improvement without modifying process steps or mask layers is reported in [52]. As illustrated in Fig. 3.16, poly gate in a dotted-channel LDMOS is intentionally drawn with open squares in layout to insert P+ diffusion regions and metal contacts (dots). When these dots are grounded through metallurgical connection, an additional parasitic resistor RX is formed (see Fig. 3.16(b)); RX is in parallel with the body resistor RB of a regular LDMOS and hence, the effective body resistance RB’ in a dotted-channel LDMOS becomes (RB // RX) to suppress the parasitic BJT.

In the dotted-channel layout, in order to open dots in transistor poly gate the gate length may need to be extended, depending on the technology node being used. Moreover, to prevent transistor breakdown voltage from being affected by the dots, the distance between

the dotted contact and the drift region has to be larger than the minimum allowable channel length [52]. These restrictions result in a negative impact to transistor RSP, and the quantity of impact is highly process-dependent. Another poly-bending layout technique that bends the poly gate in 45 degree can incorporate grounded dots as well and minimize the impact of gate lengthening to RSP [53]. In addition to the SOA improvement, both layout techniques exhibited remarkably increased secondary breakdown current to electrostatic discharges (ESD) [3].

3.4.3. Drift Configurations

It is well known that for a power MOSFET under high current conduction, the kirk effect shifts the high electric field region toward the transistor drain contacts [54]. Since the avalanche current that induces both the triggering of parasitic BJTs and the electrothermal coupling is a result of the high electric field, engineering the drift region of a power MOSFET is another approach to the SOA adjustment. A higher doping concentration in the drift region of an nLDMOS can compensate the negative electron charges during transistor on-state and hence push the onset of kirk effect to a higher current level [55]. However, increasing the doping concentration in the drift region degrades the device BVDSS as well [56].

It is well known that for a power MOSFET under high current conduction, the kirk effect shifts the high electric field region toward the transistor drain contacts [54]. Since the avalanche current that induces both the triggering of parasitic BJTs and the electrothermal coupling is a result of the high electric field, engineering the drift region of a power MOSFET is another approach to the SOA adjustment. A higher doping concentration in the drift region of an nLDMOS can compensate the negative electron charges during transistor on-state and hence push the onset of kirk effect to a higher current level [55]. However, increasing the doping concentration in the drift region degrades the device BVDSS as well [56].