Power Distribution

With the strong device self-heating involved in switching a large power MOSFET, the temperature spread across the transistor array is found to be inhomogeneous. Device edges benefit from a better thermal removal through surrounding silicon and the weak spot (highest temperature) hence locates at the center of the array [62], [69]. A uniform temperature distribution across the power transistor array that eliminates the weak spot hence improves the transistor energy capability.

From the 1-dimentional heat flow theory, a simple relationship between power dissipation, temperature increase and time is

∆ √ , (3.10) where k is thermal conductivity, is density, cp is specific heat capacity, and AE is active area.

From equation (3.10), the temperature increase is proportional to the power dissipation and the square root of time. Having different operation time among an array is less practical;

uniform power distribution across a power MOSFET array is more feasible. With the MOSFET saturation current being

, , (3.11) a multi-step layout design utilizing different current carrying capabilities is proposed to engineer the power distribution (Fig. 3.17) [69]. Power MOSFET arrays are divided into regions of different channel lengths (L) or oxide thickness. Arrows in Fig. 3.17 indicate the direction of increasing current carrying capability (shorter channel length for example).

Experimental results in [69] showed a more than 20% improvement on the energy capability and less than 10% increase on transistor turn-on resistance. Moreover, the simple single-step design was able to optimize the power distribution to its fullest already [69].

3.5. Summary

A wide SOA is required to sustain the high voltage and high current that happens across a power MOSFET at the same time, switching reactive loads for example. Through the circuit design technique, clamped inductive switching can help improve SOA when switching an inductive load. Process integration approaches such as a thick top metal layer, a heavily doped body region, or the adaptive drift implantation improve intrinsic SOA of power MOSFETs. Besides the circuit and the process integration methods, layout modifications can also enhance SOA of power MOSFETs. In summary, safe operating area is one of the most important indicators for the reliability of power MOSFETs. Research and improvement techniques on the SOA will keep continuing as an essential and critical factor in the development of power MOSFETs.

Chapter 4

High-Voltage Output Arrays and The Poly-Bending Layout for the eSOA improvement of SCR-nLDMOS

4.1. Background

For output drivers that are designed to drive considerable amount of current (output arrays), ESD design rules are usually not applied to such output arrays to minimize their layout area in silicon chips [70]. These output arrays therefore are incapable of being self-protected against ESD stresses, and some additional ESD design techniques are needed to provide adequate capabilities to survive the general ESD specification of 2-kV HBM ESD test for commercial products [3]. Additional ESD protection circuit in parallel to the output array is one of the possible design solutions, but trigger competition between the ESD protection circuit and the output array can usually lead to an upset result on ESD protection level [71].

As a result, self-protected output arrays are preferable to HV technologies. The silicon-controlled rectifier (SCR) inserting into HV output arrays has been reported as an area-efficient method to equip HV output arrays with superior ESD robustness [72]–[75].

Though embedding SCR in HV output arrays is very effective in improving ESD robustness, mis-triggering of the embedded SCR imposes new reliability concerns during normal circuit operating conditions, especially in some applications that require both high current and high drain-to-source voltages (VDS) at the same time. In [74] and [75], inserting SCR to a HV output array has been reported to diminish the SOA boundary of the output array. It is therefore important to have a more deep investigation on the impact of embedded SCR structure to the SOA of HV output arrays. In this chapter, different layout parameters and device configurations have been studied for the optimization of SOA and ESD robustness

of nLDMOS arrays in a 24-V BCD process.

(a)

(b)

Fig. 4.1. (a) Layout top view and (b) device cross-sectional view along A-A’ line of an nLDMOS without embedded SCR.

4.2. Test Structures of HV nLDMOS

Layout top view and device cross-sectional view of an nLDMOS in the 24-V process are shown in Fig. 4.1(a) and 4.1(b), respectively. The PBI layer in Fig. 4.1(b) is the optional

P-type body implantation layer. To emulate the high-current driving requirement of output arrays in practical IC products, devices were drawn in large arrays with total effective width (W) of 4800 m. Width and channel length of a single finger are kept the same in layout for all studied devices, 100 and 0.35 m, respectively.

(a)

(b)

Fig. 4.2. (a) Layout top view and (b) device cross-sectional view along B-B’-C-C’ region of an nLDMOS with embedded SCR.

To study the impact on eSOA due to embedded SCR structure, layout top view of an nLDMOS array with embedded SCR (SCR-nLDMOS) is shown in Fig. 4.2(a). Embedded SCR was centralized within the central four fingers of nLDMOS arrays by replacing part of drain implantation from N+ to P+. The four fingers that contain the embedded SCR is referred to as GateSCR fingers, and the rest 44 fingers that do not have SCR structure are referred to as GateMOS fingers. Total effective widths of SCR-nLDMOS arrays were kept the same to that of nLDMOS arrays, 4800 m. Device cross-sectional view along B-B’-C-C’

square in Fig. 4.2(a) is shown in Fig. 4.2(b). P+ implantation at drain regions is the anode of the SCR, and the SCR current path is P+  (NDD / HV N-Well) – P-body – N+ source. Gate connection for GateSCR fingers was intentionally separated from GateMOS fingers and was either internally short circuited to GateMOS fingers or internally short circuited to source/body (grounded) for further investigation. Width of a drain P+ implantation is defined as DP width.

All studied SCR-nLDMOS arrays have the same total effective SCR anode width of 200 m in the 4 GateSCR fingers. As a result, a SCR-nLDMOS with DP of 10 m means that there are 5 P+ segments in each finger, and each P+ segment is 10-m wide. The 5 P+ segments are evenly spread along the 100-m finger width. Three different DP widths of 50, 10, and 5 m, were studied in the test vehicle.

4.3. Electrical SOA of nLDMOS and SCR-nLDMOS Arrays

To analyze the impact of embedded SCR to device ruggedness under normal circuit operating conditions, eSOA with 100-ns TLP and DC gate bias was used throughout the study in this chapter. All measurements were conducted under the room temperature of 300 k.

4.3.1. PBI Layer to eSOA of nLDMOS

In an nLDMOS, the parasitic NPN BJT as indicated in Fig. 4.1(b) consists of (N+/NDD/HV N-Well) – P-body – N+ source. Rb in Fig. 1(b) denotes the parasitic resistor

from P-body without the optional PBI layer, whereas Rb’ denotes the parasitic resistor from the PBI layer. When the gate voltage is biased above 0 V, channel electrons entering a high electric field region due to a high VDS voltage can undergo the carrier multiplication process, which accelerates the electron-hole pair generation and usually leads to a reduced bipolar trigger voltage.

Fig. 4.3. Measured eSOA of nLDMOS with and without PBI layer. DUTs with IDS from low to high were measured under gate biases of 0, 3, 6, 9, 12, and 16V.

TLP-measured I-V characteristics under different gate biases and the eSOA of nLDMOS arrays with and without PBI are shown in Fig. 4.3. Because PBI layer introduces a Rb’ resistor in parallel with the P-body resistor Rb as shown in Fig. 4.1(b), base-emitter junction of the parasitic NPN BJT becomes harder to be forward biased. nLDMOS with PBI layer therefore shows a wider eSOA in Fig. 4.3 than that of nLDMOS without PBI layer [51].

Under the gate bias of 0 V (gate-grounded), measured leakage current of both nLDMOS in Fig. 4.3 immediately increased from pico-amp range to over 1 A after snapback. Measured bipolar trigger currents (It1) in Fig. 4.3 are 311 and 53 mA for gate-grounded nLDMOS with

and without PBI, respectively. Because both nLDMOS arrays failed immediately after snapback, the measured It1 values are equal to their secondary breakdown currents (It2). Both nLDMOS arrays (with and without PBI) possess a virtual zero HBM ESD protection level, therefore the embedded SCR structure becomes a necessity to provide self-protected ESD protection capability to these two nLDMOS arrays.

4.3.2. SCR-nLDMOS and DP width to eSOA (GateSCR internally short circuited to GateMOS)

With the SCR embedded in an nLDMOS array (SCR-nLDMOS), parasitic devices become more complicated than that of nLDMOS without embedded SCR. Equivalent circuit of the embedded SCR is shown in Fig. 4.4. The equivalent circuit in Fig. 4.4 resembles an insulated gate bipolar transistor (IGBT) [76], except for the RN connecting emitter and base of PNP BJT. The RN resistor comes from the N+ regions next to DP, i.e. R1 and R2 in parallel as shown in Fig. 4.2(b). Therefore, SCR-nLDMOS with a smaller DP width has a smaller equivalent RN.

Fig. 4.4. The equivalent circuit of the embedded SCR in the nLDMOS arrays.

It should be noted that in a high voltage technology where IGBT is a dedicated power device, the regenerative feedback of parasitic SCR in the IGBT is suppressed carefully to avoid latch up under normal circuit operating conditions [77]–[79]. However, for HV technologies with relatively low voltage ratings (typically < 200 V processes, so that the studied process is included, too), IGBT usually is not a dedicated device and SCR is used for ESD protection purposes. SCR structures in these technologies are made up of parasitic BJTs without being specially suppressed during process development. As a result, the sum of open-base current gains of parasitic PNP (PNP) and NPN (NPN) BJTs in these technologies can be higher than 1 to initiate regenerative feedback even under normal circuit operating conditions [80].

Measured TLP I-V curves of SCR-nLDMOS without and with PBI layer are shown in Fig.

4.5(a) and 4.5(b), respectively. Gate bias for DUTs in Fig. 4.5 was 0 V, and leakage currents were measured under the drain bias of 24 V. In Fig. 4.5(a), both SCR-nLDMOS with DP of 10 and 50 m can sustain 100-ns TLP stresses higher than the limitation of the TLP system used, 3.75A. For SCR-nLDMOS with DP of 5 m, because a smaller DP width results in a smaller RN resistor, emitter-base junction of PNP BJT becomes harder to be forward biased. As a result, DP of 5 m in Fig. 4.5(a) exhibits the highest measured trigger voltage (Vt1) of 48.62 V.

Measured Vt1 for nLDMOS without PBI in Fig. 4.3 is 49.04 V. These two measured Vt1

values of 48.62 and 49.04 V show that when DP is as small as 5 m, trigger competition can easily happen between the 4 fingers with embedded SCR (GateSCR fingers) and the other 44 fingers without embedded SCR (GateMOS fingers). As a result, instead of showing a high TLP-measured It2, SCR-nLDMOS with DP of 5 m failed (leakage current increased over 10X) at 1.31 A in Fig. 4.5(a). Because the failure arises from trigger competition between GateSCR and GateMOS fingers, a virtual zero ESD protection level on SCR-nLDMOS without PBI under DP of 5 m is possible.

(a)

(b)

Fig. 4.5. Measured TLP I-V characteristics of SCR-nLDMOS (a) without PBI and (b) with PBI.

Gate bias for all DUTs was 0 V and leakage currents were measured under 24-V drain bias.

For SCR-nLDMOS with PBI, because the measured Vt1 for gate-grounded nLDMOS with PBI in Fig. 4.3 is increased to 58.47 V, trigger competition between GateSCR and GateMOS

fingers is averted. All DUTs in Fig. 4.5(b) therefore have It2 higher than the equipment limitation of 3.75 A. Effectiveness on embedded SCR to improve ESD robustness therefore has been verified through measurement results in Fig. 4.5.

Fig. 4.6. Measured eSOA of SCR-nLDMOS with Gate_SCR short circuited to Gate_MOS. The corresponding gate biases for the IDS from low to high were 0, 3, 6, 9, 12, and 16 V, respectively.

Some measured DUTs have less than 6 data points because these DUTs under high gate biases were driven directly into SCR operation without manifesting distinct snapback to determine their eSOA boundaries.

When the potential of GateSCR is pulled high to induce channel current, electrons are provided from the N+ source (IG) and holes emitting from P+ anode of SCR can be recombined with these electrons. This is shown as J1 current flow in Fig. 4.2(b). However, instead of being recombined with electrons, part of the emitting holes from P+ anode is drawn to the vicinity of channel due to the negative charge of electrons and then be swept to the grounded P+ body contacts through the P-body/PBI (J2 current flow in Fig. 4.2(b)). These holes traveling through P-body/PBI develop a voltage drop across the base-emitter junction of NPN BJT, which will eventually trigger on NPN BJT and lead to positive regenerative feedback of SCR during normal circuit operating conditions. This can also be understood from the equivalent circuit shown in Fig. 4.4 where the IG current serves as the base current of PNP BJT and further induces the IC1 collector current [81]. Once the base-emitter junction

of NPN BJT in Fig. 4.4 is forward biased, SCR is triggered on and latchup happens.

Measured eSOA for SCR-nLDMOS without and with PBI layer are shown in Fig. 4.6.

DUTs in Fig. 4.6 have GateSCR internally connected to GateMOS, so that when a positive gate bias is applied to DUTs in Fig. 4.6, GateSCR potential is pulled high along with GateMOS

potential. Comparing eSOA shown in Fig. 4.3 and 4.6, a substantially narrowed eSOA due to embedded SCR is observed. This means by inserting SCR into nLDMOS arrays for ESD protection, the SOA boundary is changed from the triggering of NPN BJT to the triggering of SCR due to the strong positive regenerative feedback of the P-N-P-N structure.

Comparing measurement results in Fig. 4.6 with the same DP width, SCR-nLDMOS with PBI layer constantly shows a better eSOA performance than that of SCR-nLDMOS without PBI layer. This is due to the fact that PBI layer not only suppresses bipolar beta gain of NPN BJT (NPN), but also makes base-emitter junction of NPN BJT harder to be forward biased.

Measurement results in Fig. 4.6 also reveal a strong dependency of eSOA to DP width. Under the same gate and anode voltages, a smaller RN (shorter DP) helps keep the node A voltage in Fig. 4.4 at a relatively higher potential. This diminishes the emitting holes from P+ SCR anode by reducing the voltage difference across the emitter-base junction of PNP BJT. With the number of holes emitting from P+ anode being suppressed, J2 current in Fig. 4.2(b) to forward bias the base-emitter junction of NPN BJT is reduced as well. Accordingly, SCR-nLDMOS with a shorter DP width showed a better eSOA performance in Fig. 4.6.

However, combining the information from Fig. 4.5(a) and 4.6, though reducing DP width when embedding SCR to nLDMOS array is beneficial to eSOA, there is a limitation on the smallest applicable DP width which comes from the condition of trigger competition between GateSCR and GateMOS fingers.

(a)

(b)

Fig. 4.7. Measured voltage waveforms when switching a 50- resistive load under 24-V power supply voltage and a 0-to-6 V voltage pulse on gate. DUTs are (a) nLDMOS without embedded SCR and (b) SCR-nLDMOS with D_P of 50 µm. Both measured DUTs do not have the PBI layer. Gate_SCR in the measured SCR-nLDMOS is short circuited to GateMOS.

Importance of the substantially narrowed SOA to the device reliability for circuit operation is shown in Fig. 4.7(a) and 4.7(b). In Fig. 4.7(a), an nLDMOS (without PBI) was used to drive a 50- resistive load, which is common in analog circuit applications. As the measurement setup shown in the inset of Fig. 4.7(a), the 50- resistor was biased at 24 V, and a 0-to-6 V VGS pulse was applied to turn on and turn off the DUT. Measured VDS and VGS

waveforms in Fig. 4.7(a) show that the nLDMOS without PBI can safely drive the 50

resistive load. However, when doing the same 50- resistive load test on SCR-nLDMOS with DP of 50 m (without PBI), DUT was burned out after the measurement. As the measurement results shown in Fig. 4.7(b), measured VDS drops to the holding voltage of the embedded SCR (~2 V) when the DUT starts to conducting current. SCR is triggered on during the circuit switching, so that the latchup-like failure happens, and the DUT can no longer be controlled by the gate bias. Accordingly, though inserting SCR to nLDMOS has been proven to substantially increase ESD robustness, the degraded SOA should be carefully examined to avoid device failure under normal circuit operating conditions.

4.3.3. GateSCR bias to eSOA of SCR-nLDMOS (ggSCR-nLDMOS)

Because the channel current IG which induces J1 and J2 currents in Fig. 4.2(b) has been identified as one of the major sources to trigger SCR, metal connection of GateSCR was changed from being internally short circuited to GateMOS to the source/body (ggSCR-nLDMOS). This keeps IG equal to zero during normal circuit operating conditions and thus eliminates J1 and J2 in Fig. 4.2(b). Disadvantage of this ggSCR-nLDMOS configuration is obviously the reduced current driving capability, but since embedded SCR was centralized within only 4 out of 48 fingers, the reduced current driving capability can be easily compensated by increasing the total number of fingers in the output array. As the measurement results shown in Fig. 4.8, substantial improvement on eSOA was achieved simply by changing the GateSCR connection. When GateSCR was connected to GateMOS (Fig.

4.6), the measured maximum VDS ratings under 12-V gate bias for SCR-nLDMOS with PBI and DP of 5, 10, and 50 m are 15.37, 12.41, and 6.11 V, respectively. By changing the GateSCR connection to the source/body, the measured maximum VDS ratings under 12-V gate bias for DP of 5, 10, and 50 m in Fig. 4.8 are substantially increased to 37.42, 31.4, and 27.05 V, respectively.

Fig. 4.8. Measured eSOA of ggSCR-nLDMOS (Gate_SCR internally short to source/body). The corresponding gate biases for the IDS from low to high were 0, 3, 6, 9, 12, and 16 V, respectively.

Despite that GateSCR has been grounded to eliminate J1 and J2 currents, the measured eSOA boundaries in Fig. 4.8 still show a strong dependency to the gate biases. Moreover, a faster roll off on the measured VDS ratings is observed under high gate biases. For example, the measured VDS ratings in Fig. 4.8 for DP of 10 m decrease only from 38.53 to 36.53 V, when the gate bias was increased from of 3 and 9 V. However, the VDS ratings suffer a much severer degradation from 31.4 to 19.47 V, when the gate bias was increased from 12 to 16 V.

This suggests the existence of another factor affecting the triggering of embedded SCR, and this factor manifests stronger under high gate biases. In fact, because all fingers of an output array were drawn in a same HV N-Well, part of avalanche-generated electrons from GateMOS

fingers can drift through the shared HV N-Well. Since the N+ drain regions in GateSCR fingers possess the same potential to drain of GateMOS fingers, these drifting electrons can be collected by the N+ drain in GateSCR fingers. These drifting electrons collected by N+ drain in GateSCR fingers, as labeled in Fig. 4.2(b), therefore induce a voltage drop underneath the P+

anode of embedded SCR, allowing holes to emit from P+ anode. These emitting holes are

illustrated as J3 current flow in Fig. 4.2(b). J3 can be easily swept to grounded P+ body contacts to build up a voltage across base-emitter junction of the parasitic NPN BJT because of a wide depletion region in HV N-Well under high VDS voltages. For example, ggSCR-nLDMOS with DP of 50 m in Fig. 4.8 has the measured VDS rating of 18.08 V under 16-V gate bias, which is high enough to create a wide depletion region in HV N-Well in the studied 24-V process and help sweep the J3 current toward grounded P+ body contacts.

For HV nLDMOS, it has been reported that effectiveness of channel current to accelerate the carrier multiplication process under high VDS voltages can be relatively weak when gate biases are low. This comes from the mismatch on locations of the maximum current density and the maximum electric field under low gate biases. When the gate bias is high enough to induce channels underneath FOX, coincide of the channel current and the strong electric field start to accelerate the electron-hole pair generation. Therefore, it was observed that Vt1 of HV

For HV nLDMOS, it has been reported that effectiveness of channel current to accelerate the carrier multiplication process under high VDS voltages can be relatively weak when gate biases are low. This comes from the mismatch on locations of the maximum current density and the maximum electric field under low gate biases. When the gate bias is high enough to induce channels underneath FOX, coincide of the channel current and the strong electric field start to accelerate the electron-hole pair generation. Therefore, it was observed that Vt1 of HV