I/O Buffer with The New Proposed Layout Scheme (Type B)

In the type-A layout scheme, though the ballast N-Well leads to significant improvement on ESD robustness, it also introduces the (IESD × Rballast) voltage drop to ΔVPS and ΔVPD. The Rballast of N-Well resistor becomes large under high current conditions. The increased (IESD × Rballast) voltage drop pinches the ESD protection window and makes internal circuits more

susceptible to ESD failure. Even though the internal ESD failure was not observed, eliminating the Rballast term in ΔVPS and ΔVPD is also beneficial to the PS- and PD- mode ESD tests. Since the main ESD protection device in a power-rail ESD clamp circuit generally has been drawn with large device dimension, it usually stands much higher ESD stress levels than the NMOS or PMOS in I/O buffers. Furthermore, averting the PS- and PD-mode ESD current from being discharged through the Rballast can further avoid the N+-to-N-Well ESD failure.

Fig. 5.13. Diagram to show the metal connection to the I/O pad for driver NMOS and PMOS in the type-B layout scheme.

To modify the type-A layout scheme and to eliminate the Rballast term under PS- and PD-mode ESD tests, type-B layout scheme is proposed. A diagram is shown in Fig. 5.13 to illustrate the type-B layout scheme, where the N-Well ballast resistor is applied to both driver NMOS and PMOS. Drain of the driver PMOS is separated into drain diffusion and island diffusion by FOX, as shown in Fig. 5.13. Drain diffusions of driver PMOS and NMOS are connected to each other, and island diffusions of both driver PMOS and NMOS are directly

connected to the I/O pad. With such a distinct metal routing in the type-B layout scheme, the P+ island diffusion provides an efficient discharging path for PS- and PD-mode ESD tests, where ESD current can be discharged directly through the DP diode without flowing through the ballast N-Well in NMOS. The cross-sectional view along A-A’ line in Fig. 5.13 is shown in Fig. 5.14. Under the normal circuit operating conditions, with the shorted drain diffusions of driver NMOS and PMOS, PMOS can pull high the I/O pad through the ballast N-Well in the driver NMOS. Device dimensions for driver NMOS and PMOS in type-B layout scheme are the same to those in type-A layout scheme, and I/O buffers with either type-A or type-B layout scheme can meet the operating frequency specification of 20 MHz.

By avoiding ESD current to flow through the ballast N-Well under PS- and PD- mode ESD stresses, the ESD currents are mainly discharged through the diode DP1 and the power-rail ESD clamp circuit (in PS-mode). As the PS- and PD- mode TLP-measured I-V curves shown in Fig. 5.15, high resistance characteristic from the ballast N-Well in type-A layout scheme is avoided in the type-B layout scheme. Therefore, ΔVPS and ΔVPD in the type-B layout scheme are much smaller compared to those in the type-A layout scheme. Under ND-mode and NS-mode conditions, the DN diode and the power-rail ESD clamp circuit are effective in discharging ESD currents, as shown in Fig. 5.15.

Fig. 5.14. Cross-sectional view along A-A’ line of the fully-silicided I/O buffer realized with the type-B layout scheme.

Fig. 5.15. TLP-measured I-V curves for the I/O buffer with the type-B layout scheme. The tests were manually stopped at 2 A without causing failure to the I/O buffer.

Because the ESD current can be discharged without flowing through the ballast N-Well in the driver NMOS, the N+-to-N-Well ESD failure on driver NMOS is avoided in the type-B layout scheme. Moreover, the N-Well can ballast the driver NMOS when ΔVPS or ΔVPS is higher than Vt1,MN1. PS-mode HBM ESD robustness of the I/O buffer has therefore been increased to 7 kV, and the PD-mode HBM ESD robustness has been increased to over 8 kV, as shown in Table I. Emission microscope (EMMI) analysis in Fig. 5.16(a) shows that failure of the I/O buffer with the type-B layout scheme after 7.5-kV PS-mode ESD stress locates on the driver PMOS. The corresponding SEM image of the failure on the driver PMOS in Fig.

5.16(a) is shown in Fig. 5.16(b). Without the ESD damage on source but silicides meltdown on island diffusions, SEM image reveals the PS-mode ESD failure on the P+/N-Well diode (DP) of driver PMOS, which has further confirmed that the type-B layout scheme has taken advantage of the highest whole-chip ESD protection capability from the I/O buffers.

(a)

(b)

Fig. 5.16. (a) EMMI and (b) SEM images of the fully-silicided I/O buffer realized with the type-B layout scheme after 7.5-kV PS-mode ESD stress.

5.5. Summary

Silicidation used in CMOS processes has been reported to cause substantial degradation on ESD robustness of CMOS devices. To mitigate the negative impact on ESD robustness from silicidation, two new ballasting layout schemes for fully-silicided I/O buffers are proposed.

The new proposed ballasting layout schemes have been verified on a real IC product fabricated in a 0.35-m 5-V fully-silicided CMOS process. Without adequate ballasting technique in the original layout, the fully-silicided I/O buffer has a very poor ESD level of 1.5 kV in HBM ESD tests. Ballast N-Well on the driver NMOS is useful to avoid PS-mode ESD failure on NMOS, but the ND-mode ESD failure over the un-ballasted driver PMOS limits the ESD robustness to only 4 kV. With the proposed type-A layout scheme, the whole-chip ESD protection level has been improved to the performance target of 6-kV HBM ESD robustness. The proposed type-B layout scheme further increases the whole-chip ESD robustness up to 7 kV. No additional mask or process step are required to fulfill either one of the new proposed layout schemes. The new proposed ballasting layout schemes are process-portable to different CMOS technologies. Moreover, the type-B layout scheme ballasts I/O buffers without imposing the ballast resistance on the ESD protection window.

With the new proposed ballasting layout schemes, the additional mask and process steps for silicide blocking can be omitted to reduce the fabrication cost without sacrificing the ESD robustness of IC products.

Chapter 6

Fully-Silicided ESD Protection Design on The Voltage Programming Pins of ICs with One-Time Programming Memories

6.1. Background

One-time programming (OTP) read only memory (ROM) has been widely implemented in micro-controllers (MCUs) [118]. To successfully program the memory cells, a HV on the voltage programming (VPP) pin is necessary to induce channel hot electrons or to burn out the fuse [119], [120]. Because the programming voltage (VPP voltage) is higher than the VDD

normal operating voltage of internal circuits, current paths from the VPP pin to the VDD power supply line is unallowable. With the forbidden current path from VPP pin to the VDD power supply line, such a VPP pin suffers a stringent challenge on ESD protection design.

With silicide blocking (SB) being omitted in the studied process of this chapter, novel fully-silicided design for the VPP pin ESD protection is necessary. The open-drain structure further increases the ESD design challenge. An efficient ESD protection design for fully-silicided ICs with voltage programming pin is therefore a highly challenging reliability issue to IC designers [121]–[124]. Moreover, to make the MCUs universally compatible to different ROM programmers, VPP-pin ESD protection designs are often required to have high immunity against fast voltage transition during memory programming.

In this chapter, a new ESD protection design for fully-silicided VPP pin is proposed, including a circuit design to avoid the mis-triggering of ESD protection device during the programming conditions when VPP voltage has a fast rise time. The proposed ESD protection design has been successfully verified on a commercial IC product with OTP memory cells in a 0.35-m fully-silicided CMOS process.

(a)

(b)

(c)

Fig. 6.1. (a) Normal operating condition of the memory unit before programmed. Channel can be induced under V_GS of 5 V and V_DS of 5 V. (b) Bias conditions of the memory unit during programming.

A high control gate bias of 12.5 V is used to draw channel hot electrons into the floating gate. (c) Normal operating condition of the memory unit after programmed. Channel cannot be induced under V_GS of 5 V and V_DS of 5 V due to the trapped electrons in the floating gate.