8. Conclusions and Future Works
8.2 Future Works
For the operation of power MOSFETs, it is very often that the transistors’ drain or ground potentials be perturbed greatly, especially when switching with a large current. Noise immunity of the nLDMOS transistors and the impact that comes from the SCR insertion is an important future work thereof. A challenge to this study would be the fact that noises from different systems or applications are case-sensitive, and presently there is no unified standard or platform suitable for device-level measurements. Testing ICs on their system boards is necessary for this noise study on power MOSFETs.
The VPP pin ESD protection design in Chapter 6 has the lowest potential of 0 V because of its application specifications. For ICs with their lowest voltage potentials below 0 V, e.g.
NAND memories, the ESD protection design along with its trigger circuit should be modified and it would be both interesting and useful to implement such an application-oriented ESD protection design.
With the high power supply voltages in HV applications, latchup is an extremely challenging reliability topic. Designing a structure with high latchup immunity has been an important development target in HV ICs for decades. From the research results in Chapter 7, the challenge becomes more stringent and correct measurement techniques to evaluate the latchup immunity of HV transistors are equally important. With the new observed phenomenon, latchup in HV ICs will face new challenges; new physical mechanisms to be discovered as well. Accordingly, latchup is a topic not only intriguing but also valuable to the IC industries, and worthy to put further efforts for future works and developments.
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