[PDF] Top 20 A novel Si-B diffusion source for p(+)-poly-Si gate
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A novel Si-B diffusion source for p(+)-poly-Si gate
... Inc. A p 1 -poly-Si gate has been proposed for the fabrication of sur- face-channel p-metal oxide semiconductor field effect transistors (p- MOSFETs) in deep ... See full document
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Novel Sub-10-nm Gate-All-Around Si Nanowire Channel Poly-Si TFTs With Raised Source/Drain
... with a channel length of ...supply gate voltage, and higher I ON /I OFF ratio than the ...of poly-Si TFTs can be improved if the poly-Si grain size can be enhanced and the number ... See full document
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A novel laser-processed self-aligned gate-overlapped LDD poly-Si TFT
... Abstract—A novel process for fabricating self-aligned gate-over- lapped LDD (SAGOLDD) poly-Si thin film transistors (TFTs) was ...irradiation for dopant activation was ... See full document
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A Novel Scheme for Fabricating CMOS Inverters With Poly-Si Nanowire Channels
... Abstract—A novel complementary metal–oxide–semiconductor inverter with poly-Si nanowire channels is proposed and demon- strated in this ...employs a clever tilted-angle implant process ... See full document
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Novel gate-all-around poly-Si TFTs with multiple nanowire channels
... Abstract—The novel gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with multiple nanowire channels (MNCs) have been, for the first time, fabricated using a simple ... See full document
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The reaction of Co and Si1-xGex for MOSFET with poly-Si1-xGex gate
... Standard poly-Si plasma etch recipe was then used to pat- tern the poly-Si 1 −x Ge x ...The source/drain junctions were formed by BF 2 implantation. After a cleaning step and HF ... See full document
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High-performance RSD poly-Si TFTs with a new ONO gate dielectric
... RSD Poly-Si TFTs With a New ONO Gate Dielectric Kow-Ming Chang, Member, IEEE, Wen-Chih Yang, and Bing-Fang Hung Abstract—This paper developed a novel polycrystalline silicon ... See full document
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A Novel Charge-Trapping-Type Memory With Gate-All-Around Poly-Si Nanowire and HfAlO Trapping Layer
... the gate-all-around (GAA) configuration is known to enhance the gate controllability and the tunneling probability through the tunnel oxide because of the increase in the surface curvature of the wrapped ... See full document
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A novel process to form cobalt silicided p(+) poly-Si gates by BF2+ implantation into bilayered CoSi/a-Si films and subsequent anneal
... curves for the specimens with poly-Si, CoSi/poly, and CoSi/a-Si films, respectively, annealed at 900 C for 60 ...addition, a significant capacitance reduction ... See full document
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A novel germanium doping method for fabrication of high-performance p-channel poly-Si1-xGex TFT by excimer laser crystallization
... ELC poly-Si by LPCVD at 450 C, respectively. The a-Si Ge was then subjected to the second excimer laser irradiation with a shot density of 10 shots per area (90% ...of ... See full document
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Investigation of p-type junction-less independent double-gate poly-Si nano-strip transistors
... control gate bias for the J-less IDG nano- strip transistors operating in single-gate ...Conclusion A novel p-type poly-Si nano-strip IDG J-less transistor ... See full document
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The Degradation of MILC P-Channel Poly-Si TFTs under Dynamic Hot-Carrier Stress Using a Novel Test Structure
... structure a thin 5 nm Ni layer was deposited by ...in a furnace at 540 o C for 24 hours in N 2 ...Afterwards, a 30 nm-thick silicon oxide layer was deposited by PECVD, followed by the ... See full document
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A novel nanowire channel poly-Si TFT functioning as transistor and nonvolatile SONOS memory
... layers for the standard TFT ...to gate electrode. The injection of electrons from the gate to the storage layer during the erasing operation causes inefficient erasing and a lower threshold ... See full document
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Sloped-Gate Voltage Method for Improving Measurement of Poly-Si Nanowire FET in Aqueous Environment
... and source long after switching V GS ...fficient for the fit is ...pF for V GS switching from 0 to ...phenomenon for measurements done while switching V GS at low gate ... See full document
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Read Characteristics of Independent Double-Gate Poly-Si Nanowire SONOS Devices
... IDG poly-Si NW SONOS devices are ...control gate as the gate of the charge storage side is used as the driving gate for sensing V th ...finding, a novel scheme ... See full document
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In Situ Doped Source/Drain for Performance Enhancement of Double-Gated Poly-Si Nanowire Transistors
... improvement for the two SG modes is related to their different current paths from the source to the ...across a long distance of only moderately doped S/D before reaching the topmost portion of S/D ... See full document
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A novel process-compatible fluorination technique with electrical characteristic improvements of poly-Si TFTs
... First, a 100-nm-thick amorphous silicon layer was deposited on a thermally oxidized Si wafer by dissociation of SiH gas in a low-pressure chemical vapor deposition (LPCVD) system at 550 ... See full document
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A Novel SONOS Memory With Recessed-Channel Poly-Si TFT via Excimer Laser Crystallization
... and a 100-nm-thick in situ phosphorus-doped polysili- con layer were formed by ...the gate electrodes, a self-aligned phosphorous implantation with a dose of 5 × 10 15 cm −2 was carried out to ... See full document
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Investigation of source-follower type analog buffer using low temperature poly-Si TFTs
... thirty poly-Si transistors fabricated in the factory and Fig. 1b shows the field-effect mobility ...necessary for a poly-Si TFT-LCD, it is very essential to develop ... See full document
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A novel four-mask-processed poly-Si TFT fabricated using excimer laser crystallization of an edge-thickened alpha-Si active island
... First, a 93-nm-thick -Si layer was deposited on thermally oxidized ...m-thick) Si wafers by decomposing SiH in a low-pressure chemical vapor deposition (LPCVD) system at 550 ...Next, a ... See full document
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