[PDF] Top 20 A 2 V clock synchronizer using digital delay-locked loop
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A 2 V clock synchronizer using digital delay-locked loop
... It consists of an improved bang-bang type phase comparator, a set of control logic, a 6-bit up/down counter, a digital controlled delay line (DCDL).. and on-chip receivers and d[r] ... See full document
4
A Wide-Range Delay-Locked Loop with a Fixed Latency of One Clock Cycle
... one clock cycle is proposed by using the phase selection circuit and the start-controlled ...the delay equal to one clock cycle but also operates without the restrictions stated ...Fig. ... See full document
3
An all-digital phase-locked loop for high-speed clock generation
... with a novel fine-tuning delay cell is ...building a high-resolution cell-based ...silicon using TSMC ...has a frequency range of 45–510 MHz with DCO resolution better than 5 ... See full document
5
An all-digital phase-locked loop (ADPLL)-based clock recovery circuit
... both clock recovery and a frequency synthesizer into a single sys- ...if a system includes several modules to process received information in parallel and the final data must be combined, ... See full document
11
A wide-range and fast-locking all-digital cycle-controlled delay-locked loop
... ONCLUSION A wide-range and fast-locking all-digital DLL is presented in this ...by a factor of without decreasing timing ...input clock within 32 clock cycles regardless of the input ... See full document
10
A Differentially Coherent Delay-Locked Loop for Spread Spectrum Tracking Receivers
... Correlator, delay-locked loop, direct sequence spread spectrum, tracking error ...present a code tracking receiver with less complexity, by employing a differentially coherent tech- ... See full document
3
Piezoelectric-transducer-based optoelectronic frequency synchronizer for control of pulse delay in a femtosecond passively mode-locked Ti : sapphire laser
... eliminate a nonlinear transfer function in an an- alog phase-shifting scheme, a modified phase-locked loop 共PLL兲 technology has produced a digital and pro- grammable phase ... See full document
6
Phase-locked-loop-based delay-line-free picosecond electro-optic sampling system
... Subsequently, a delay-time-tunable picosecond Nd:YAG laser has been proposed by employing the phase-shifting technology 7 to amend the aforementioned problems in a con- ventional EOS ...to a ... See full document
8
A Low-Power 2.4-GHz CMOS GFSK Transceiver With a Digital Demodulator Using Time-to-Digital Conversion
... in a digital demodulator for a low-power ...employs a self-sampling technique and an auto-calibration algo- rithm to avoid edge synchronization problems and the need of a ... See full document
11
A Low-Power DCO Using Interlaced Hysteresis Delay Cells
... presents a low-power small-area digitally controlled oscillator ...binary-weighted delay stages is applied for the delay range and resolution ...hysteresis delay cell, which is power and area ... See full document
5
A 2-V, 1.8-GHz BJT phase-locked loop
... The loop filter consists of a pole generator and a zero generator, The schematic of the pole generator is shown in ...be a type-I signal, and the UD input a type-II ...is a ... See full document
6
The Design of a K-Band 0.8-V 9.2-mW Phase-Locked Loop
... under a 0.8-V power supply. The DPF-VCO and CCMILFD consume 5.2 mA whereas the rest of circuits such as PFD, complementary charge pump, and CML dividers consume ... See full document
6
A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18-mu m CMOS for V-Band Applications
... paper, a novel CMOS phase-locked loop (PLL) integrated with an injection-locked frequency multiplier (ILFM) that generates the -band output signal is ...the loop gain smaller than unity ... See full document
8
Multi-Rating Electronic Ballast for Fluorescent Lamp Using Phase-Locked Loop Control Scheme
... Keywords-multi-rating; ballast; fluorescent; phase-locked loop; resonant I. I NTRODUCTION The fluorescent lamps are accepted as one of the highest power efficiency lamp. These lamps are widely used in many ... See full document
6
A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator
... input reference clock CK,<,and delayed clock from the last stage of delay line CKVcd, by digital phase detector which signals the following digital code generator to generat[r] ... See full document
4
A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay
... 2 to Vdd, the proposed phase detector and the current pump circuit will discharge the loop filter to increase the delay of the VCDL.. It will align the phases between the input c[r] ... See full document
4
Performance analysis of noncoherent digital delay locked loops for direct sequence spread spectrum systems with Doppler shift and quantized adaptation
... all digital modem implementation of DSSS ...second-order digital code tracking loops is investigated over AWGN channels with the presence of Doppler ...on a regenerative Markov chain modeling of the ... See full document
11
Low jitter Butterworth delay-locked loops
... Modern CMOS techniques can not only integrate many digital circuits into a system, but also raise the operating clock frequency of the digital systems. However, the higher opera[r] ... See full document
4
A 2 V CMOS programmable pipelined digital differential matched filter for DS-CDMA system
... Pipelined Digital Differential Matched Filter The total number of multiplication and summation in conventional matched filter M, is 2'-1, where r is the order of the PN code[r] ... See full document
2
A new DLL-based approach for all-digital multiphase clock generation
... in a standard ...with delay cells pro- vided in the cell library. In those delay cells, the MOS channel length is longer than in normal ...larger delay than normal cells. The delay time ... See full document
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