[PDF] Top 20 Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers
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Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers
... Electrostatic Discharge Protection Design for Mixed-Voltage CMOS I/O Buffers Ming-Dou Ker, Senior Member, IEEE, and Chien-Hui Chuang Abstract—A ... See full document
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Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: Design concept and circuit implementations
... gate voltage (Vg1) of Mn1 at ...ESD protection circuit can meet the electrical-field constraint of gate-oxide relia- bility under normal circuit operating ...initial voltage level on the floating VDD ... See full document
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Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs
... programming voltage on pin, the place- ment of ESD diode from I/O pad to is prohibited, which results in a stringent ESD design challenge for ...programming voltage could be as ... See full document
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Overview and design of mixed-voltage I/O buffers, with low-voltage thin-oxide CMOS transistors
... AND DESIGN OF MIXED-VOLTAGE I/O BUFFER 1943 TABLE III C OMPARISON IN A REA (D EVICE S IZES ) A MONG THE M IXED -V OLTAGE I/O B UFFERS of stacked configuration are twice as ... See full document
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ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers
... VLSI Design Division of the Computer and Communica- tion Research Laboratories (CCL), Industrial Tech- nology Research Institute (ITRI), ...quality design for circuits and systems in CMOS ... See full document
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ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit
... VLSI Design Department, Computer and Communication Research Labo- ratories (CCL), Industrial Technology Research Institute (ITRI), Taiwan, ...VLSI Design Division, ...ESD protection design and ... See full document
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A floating gate design for electrostatic discharge protection circuits
... Similar design is also observed in ...useful for the ESD robustness enhancement. We have discussed leakage problem for the scaled down ...threshold voltage becomes lowering while the ... See full document
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New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology
... power-rail electrostatic discharge (ESD) clamp circuit realized with only thin gate oxide 1-V (1 × VDD) devices and a silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and ... See full document
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On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in subquarter-micrometer CMOS process
... stacked-nMOS for conducting large amounts of ESD current involves both avalanche breakdown and turn-on of the parasitic lateral bipolar ...The voltage level, where the local substrate potential is elevated, ... See full document
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Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology
... ESD protection designs for the mixed-voltage I/O circuits without suffering the gate-oxide reliability ...the mixed-voltage I/O circuits, the ESD ... See full document
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Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits
... scaled-down CMOS technologies, the power-supply voltages in CMOS ICs have been also scaled downwards to follow the constant-field scaling requirement and to reduce power ...consumption. For ... See full document
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Transient-to-Digital Converter for System-Level Electrostatic Discharge Protection in CMOS ICs
... proposed for the first time in the literature to detect the fast electrical transients and convert them to digital thermometer codes under system- level ESD ...0.18-µm CMOS process with ...ESD ... See full document
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An optimal silicidation technique for electrostatic discharge protection sub-100 nm CMOS devices in VLSI circuit
... silicide design consideration for electrostatic discharge (ESD) protection in nanoscale CMOS ...efficiency for various conditions; in particular, for optimizing the ... See full document
5
Design of mixed-voltage I/O buffer by using NMOS-blocking technique
... quality design for nanoelectronics and gigascale systems, high-speed or mixed-voltage I/O interface circuits, special sensor circuits, and thin-film transistor (TFT) ...quality ... See full document
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Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board
... is off. The gate voltage of Mp_out will be dropped down to induce leakage current between I/O pads when the power of VDD is ...the I/O ...some mixed-voltage ... See full document
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Design of Mixed-Voltage-Tolerant Crystal Oscillator Circuit in Low-Voltage CMOS Technology
... quality design for integrated circuits by hundreds of design houses and semiconductor companies in the worldwide IC ...Editor for the IEEE T RANSACTIONS ON V ERY L ARGE S CALE I ... See full document
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Design of High-Voltage-Tolerant ESD Protection Circuit in Low-Voltage CMOS Processes
... trigger voltage of ESD clamp ...circuit for both two 3 × VDD-tolerant ESD clamp ...VDD mixed-voltage I/O buffer can be significantly increased up to 8 kV with the proposed ESD ... See full document
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ESD protection design of low-voltage-triggered p-n-p devices and their failure modes in mixed-voltage I/O interfaces with signal levels higher than VDD and lower than VSS
... salicided CMOS process is higher than that in the 0.35-µm polycided CMOS process, the junctions have slightly lower breakdown voltages in the ...0.25-µm CMOS process than that in the ...0.25-µm ... See full document
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Effective electrostatic discharge protection circuit design using novel fully silicided N-MOSFETs in sub-100-nm device era.
... Except for the device area and response time, the driving capability is also an important issue when designing the output ...output buffers conventionally are fabricated by using the silicide-blocked ... See full document
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Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation
... proposed I/O and prior arts The power consumption is compared in Table 6 with ...m CMOS model, and the root-mean-square (rms) current of the supply voltage is adopted as ...ns for 150 ... See full document
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