[PDF] Top 20 The Design of a K-Band 0.8-V 9.2-mW Phase-Locked Loop
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The Design of a K-Band 0.8-V 9.2-mW Phase-Locked Loop
... received the B.S. and MS degrees from the Department of Electronics Engineering, Na- tional Chiao Tung University, Hsinchu, Taiwan, ...Department of Electrical Engineer- ing, University ... See full document
6
A 2-V, 1.8-GHz BJT phase-locked loop
... The loop filter consists of a pole generator and a zero generator, The schematic of the pole generator is shown in ...Fig. 8, which basically is an ... See full document
6
A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18-mu m CMOS for V-Band Applications
... paper, a novel CMOS phase-locked loop (PLL) integrated with an injection-locked frequency multiplier (ILFM) that generates the -band output signal is ...Since the ... See full document
8
Design of 24-GHz 0.8-V 1.51-mW Coupling Current-Mode Injection-Locked Frequency Divider With Wide Locking Range
... Abstract—A 0.8-V CMOS coupling current-mode injec- tion-locked frequency divider (CCMILFD) with ...and a current-injection current-mode logic (CICML) fre- quency divider have ... See full document
11
Applicability of phase-locked loop to tracking the rhythmic activity in EEGS
... When the PLL is applied to detection of the dominant frequency in a multi- frequency input signal, its performance is affected by the magnitude ratio of the do[r] ... See full document
16
THE OPTICAL SIGNAL GENERATOR AND PHASE-LOCKED LOOP BASED ON A TRIANGULARLY PHASE-MODULATED FIBEROPTIC GYROSCOPE
... to the accuracy, completeness, or suitability for any purpose of the ...are the opinions and views of the authors, and are not the views of or endorsed by Taylor & ... See full document
7
A Time-Based Frequency Band Selection Method for Phase-Locked Loops
... frequency band selection method for phase-locked loops ...High-performance phase-locked loops (PLLs) often require voltage- controlled oscillators (VCOs) employing both discrete and ... See full document
2
A Low-Phase-Noise K-Band CMOS VCO
... The design and analysis of the proposed VCO topology are presented in Section ...Finally, the conclusion follows in Section IV. Manuscript received January 9, 2006; revised March ... See full document
3
The Design and Simulations of Phase and Timing Tracking Circuits with Pre-assured 2nd order Digital Loop Filter
... Keywords- Phase tracking circuit;Timing tracking circuit;pre- assured 2 nd order digital loop filter;convergence triangle ...NTRODUCTION The importance of synchronization circuits in ... See full document
4
Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology
... was a Department Manager with the VLSI Design Division, Computer and Communication Re- search Laboratories, Industrial Technology Research Institute, ...been a Full Professor with the ... See full document
6
Impact of gate tunneling leakage on performances of phase locked loop circuit in nanoscale CMOS technology
... Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan A BSTRACT The influence of gate tunneling leakage on the circuit performances of phase ... See full document
2
A 160-GHz Frequency-Translation Phase-Locked Loop With RSSI Assisted Frequency Acquisition
... by the RSSI and level detector, this pull-in process will be finished when the signal amplitude at exceeds the threshold level to drive the succeeding frequency ...this design, ... See full document
8
An all-digital phase-locked loop for high-speed clock generation
... for the target frequency. The frequency acquisition starts from the middle frequency band of the ...frequencies, the search step is in the ini- tial state. When ... See full document
5
Multi-Rating Electronic Ballast for Fluorescent Lamp Using Phase-Locked Loop Control Scheme
... fluorescent; phase-locked loop; resonant I. I NTRODUCTION The fluorescent lamps are accepted as one of the highest power efficiency ...organizations. The very weak point ... See full document
6
An all-digital phase-locked loop (ADPLL)-based clock recovery circuit
... structure of the phase and frequency estimator is shown in ...new phase and period (frequency), the function of clock recovery is similar to ...Both phase error and ... See full document
11
A Wide-Range Delay-Locked Loop with a Fixed Latency of One Clock Cycle
... latency of one clock cycle is proposed by using the phase selection circuit and the start-controlled ...circuit. The proposed DLL not only locks the delay equal to one clock ... See full document
3
Design of Dual-Band Coupler With Arbitrary Power Division Ratios and Phase Differences
... for the first time, a directional coupler that allows for arbitrary power division ratios as well as arbitrary phase differences at dual frequencies of ...Explicit design equations in ... See full document
10
Genetic algorithm-based fuzzy pulse-pump controller for phase/frequency-locked Loop servomechanism
... The WIAE can actually provide good performance index for tuning variables of the presented The convergent performance of the elitist selection strategy, roulette whe[r] ... See full document
6
A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator
... input reference clock CK,<,and delayed clock from the last stage of delay line CKVcd, by digital phase detector which signals the following digital code generator to generat[r] ... See full document
4
A 2 V clock synchronizer using digital delay-locked loop
... It consists of an improved bang-bang type phase comparator, a set of control logic, a 6-bit up/down counter, a digital controlled delay line (DCDL).. and on-chip receivers and d[r] ... See full document
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